8000 Extend SPI support to fully support all SPI devices on STM32F429. Add… · micropython/micropython@4e7d051 · GitHub
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Tobias Badertscher
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Extend SPI support to fully support all SPI devices on STM32F429. Added example python script to read MEMs on STM32F429-DISCOVERY.
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‎stmhal/boards/STM32F429DISC/l3gd20.py

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"""
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Driver for accelerometer on STM32F429 Discover board.
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Sets accelerometer range at +-2g.
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Returns list containing X,Y,Z axis acceleration values in 'g' units (9.8m/s^2).
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See:
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STM32Cube_FW_F4_V1.1.0/Drivers/BSP/Components/l3gd20/l3gd20.h
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STM32Cube_FW_F4_V1.1.0/Drivers/BSP/Components/l3gd20/l3gd20.c
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STM32Cube_FW_F4_V1.1.0/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery.c
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STM32Cube_FW_F4_V1.1.0/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery.h
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STM32Cube_FW_F4_V1.1.0/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_accelerometer.c
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STM32Cube_FW_F4_V1.1.0/Drivers/BSP/STM32F4-Discovery/stm32f4_discovery_accelerometer.h
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STM32Cube_FW_F4_V1.1.0/Projects/STM32F4-Discovery/Demonstrations/Src/main.c
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"""
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from pyb import Pin
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from pyb import SPI
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import struct
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#
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# General SPI
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#
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L3GD20_READWRITE_CMD = const(0x80)
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L3GD20_MULTIPLEBYTE_CMD = const(0x40)
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#
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# Constants for the SPI device.
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#
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L3GD20_WHO_AM_I_ADDR = const(0x0F) # device identification register
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L3GD20_CTRL_REG1_ADDR = const(0x20) # Control register 1
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L3GD20_CTRL_REG2_ADDR = const(0x21) # Control register 2
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L3GD20_CTRL_REG3_ADDR = const(0x22) # Control register 3
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L3GD20_CTRL_REG4_ADDR = const(0x23) # Control register 4
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L3GD20_CTRL_REG5_ADDR = const(0x24) # Control register 5
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L3GD20_REFERENCE_REG_ADDR = const(0x25) # Reference register
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L3GD20_OUT_TEMP_ADDR = const(0x26) # Out temp register
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L3GD20_STATUS_REG_ADDR = const(0x27) # Status register
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L3GD20_OUT_X_L_ADDR = const(0x28) # Output Register X
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L3GD20_OUT_X_H_ADDR = const(0x29) # Output Register X
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L3GD20_OUT_Y_L_ADDR = const(0x2A) # Output Register Y
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L3GD20_OUT_Y_H_ADDR = const(0x2B) # Output Register Y
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L3GD20_OUT_Z_L_ADDR = const(0x2C) # Output Register Z
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L3GD20_OUT_Z_H_ADDR = const(0x2D) # Output Register Z
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L3GD20_FIFO_CTRL_REG_ADDR = const(0x2E) # Fifo control Register
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L3GD20_FIFO_SRC_REG_ADDR = const(0x2F) # Fifo src Register
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L3GD20_INT1_CFG_ADDR = const(0x30) # Interrupt 1 configuration Register
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L3GD20_INT1_SRC_ADDR = const(0x31) # Interrupt 1 source Register
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L3GD20_INT1_TSH_XH_ADDR = const(0x32) # Interrupt 1 Threshold X register
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L3GD20_INT1_TSH_XL_ADDR = const(0x33) # Interrupt 1 Threshold X register
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L3GD20_INT1_TSH_YH_ADDR = const(0x34) # Interrupt 1 Threshold Y register
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L3GD20_INT1_TSH_YL_ADDR = const(0x35) # Interrupt 1 Threshold Y register
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L3GD20_INT1_TSH_ZH_ADDR = const(0x36) # Interrupt 1 Threshold Z register
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L3GD20_INT1_TSH_ZL_ADDR = const(0x37) # Interrupt 1 Threshold Z register
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L3GD20_INT1_DURATION_ADDR = const(0x38) # Interrupt 1 DURATION register
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L3GD20_I_AM_L3GD20 = const(0xD4)
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L3GD20_I_AM_L3GD20_TR = const(0xD5)
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L3GD20_MODE_POWERDOWN = const(0x00)
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L3GD20_MODE_ACTIVE = const(0x08)
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L3GD20_OUTPUT_DATARATE_1 = const(0x00)
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L3GD20_OUTPUT_DATARATE_2 = const(0x40)
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L3GD20_OUTPUT_DATARATE_3 = const(0x80)
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L3GD20_OUTPUT_DATARATE_4 = const(0xC0)
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L3GD20_X_ENABLE = const(0x02)
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L3GD20_Y_ENABLE = const(0x01)
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L3GD20_Z_ENABLE = const(0x04)
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L3GD20_AXES_ENABLE = const(0x07)
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L3GD20_AXES_DISABLE = const(0x00)
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L3GD20_BANDWIDTH_1 = const(0x00)
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L3GD20_BANDWIDTH_2 = const(0x10)
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L3GD20_BANDWIDTH_3 = const(0x20)
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L3GD20_BANDWIDTH_4 = const(0x30)
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L3GD20_FULLSCALE_250 = const(0x00)
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L3GD20_FULLSCALE_500 = const(0x10)
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L3GD20_FULLSCALE_2000 = const(0x20)
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L3GD20_FULLSCALE_SELECTION = const(0x30)
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L3GD20_SENSITIVITY_250DPS = 8.75 #!< gyroscope sensitivity with 250 dps full scale [DPS/LSB]
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L3GD20_SENSITIVITY_500DPS = 17.50 #!< gyroscope sensitivity with 500 dps full scale [DPS/LSB]
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L3GD20_SENSITIVITY_2000DPS = 70.00 #!< gyroscope sensitivity with 2000 dps full scale [DPS/LSB]
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L3GD20_BlockDataUpdate_Continous = const(0x00)
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L3GD20_BlockDataUpdate_Single = const(0x80)
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L3GD20_BLE_LSB = const(0x00)
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L3GD20_BLE_MSB = const(0x40)
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L3GD20_HIGHPASSFILTER_DISABLE = const(0x00)
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L3GD20_HIGHPASSFILTER_ENABLE = const(0x10)
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L3GD20_INT1 = const(0x00)
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L3GD20_INT2 = const(0x01)
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L3GD20_INT1INTERRUPT_DISABLE = const(0x00)
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L3GD20_INT1INTERRUPT_ENABLE = const(0x80)
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L3GD20_INT2INTERRUPT_DISABLE = const(0x00)
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L3GD20_INT2INTERRUPT_ENABLE = const(0x08)
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L3GD20_INT1INTERRUPT_LOW_EDGE = const(0x20)
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L3GD20_INT1INTERRUPT_HIGH_EDGE = const(0x00)
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L3GD20_BOOT_NORMALMODE = const(0x00)
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L3GD20_BOOT_REBOOTMEMORY = const(0x80)
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L3GD20_HPM_NORMAL_MODE_RES = const(0x00)
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L3GD20_HPM_REF_SIGNAL = const(0x10)
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L3GD20_HPM_NORMAL_MODE = const(0x20)
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L3GD20_HPM_AUTORESET_INT = const(0x30)
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L3GD20_HPFCF_0 = const(0x00)
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L3GD20_HPFCF_1 = const(0x01)
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L3GD20_HPFCF_2 = const(0x02)
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L3GD20_HPFCF_3 = const(0x03)
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L3GD20_HPFCF_4 = const(0x04)
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L3GD20_HPFCF_5 = const(0x05)
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L3GD20_HPFCF_6 = const(0x06)
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L3GD20_HPFCF_7 = const(0x07)
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L3GD20_HPFCF_8 = const(0x08)
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L3GD20_HPFCF_9 = const(0x09)
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#
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# Default configuration:
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# Output data rate 190 Hz
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# Bandwidth/Cut off 50 Hz
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L3GD20_CTRL_REG1_VAL = const(0b01101111)
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# Normal Mode
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# Highpass cut-off 0.018Hz
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L3GD20_CTRL_REG2_VAL = const(0b00001001)
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# No interrupts
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L3GD20_CTRL_REG3_VAL = const(0b00000000)
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# Continous block update
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# Little endinan data
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# Full scale is 250 dps (degrees per second)
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# Use 4 wire SPI
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L3GD20_CTRL_REG4_VAL = const(0b00000000)
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# Normal Mode
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# FIFO is enabled
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# No Highpass
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# Int1/int2:00
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#
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L3GD20_CTRL_REG5_VAL = const(0b01000000)
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class L3GD20:
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#
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# Debug
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#
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DEFAULT_CONF = [
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(L3GD20_CTRL_REG1_ADDR, L3GD20_CTRL_REG1_VAL),
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(L3GD20_CTRL_REG2_ADDR, L3GD20_CTRL_REG2_VAL),
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(L3GD20_CTRL_REG3_ADDR, L3GD20_CTRL_REG3_VAL),
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(L3GD20_CTRL_REG4_ADDR, L3GD20_CTRL_REG4_VAL),
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(L3GD20_CTRL_REG5_ADDR, L3GD20_CTRL_REG5_VAL)]
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DEBUG = False
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def __init__(self, spiNr=5):
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self._conf={}
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self.cs_pin = Pin('PC1', Pin.OUT_PP, Pin.PULL_NONE)
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self.cs_pin.high()
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self.spi = SPI(spiNr, SPI.MASTER, baudrate=328125, polarity=1, phase=1, bits=8)
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self.who_am_i = self.read_id()
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if self.who_am_i == L3GD20_I_AM_L3GD20:
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for addr, val in L3GD20.DEFAULT_CONF:
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self.write_bytes(addr, bytearray([val,]))
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self._conf[addr] = val
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else:
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raise Exception('L3GD20 gyro not present')
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self.updateDpsFS()
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def updateDpsFS(self):
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conv = {
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L3GD20_FULLSCALE_250 : 250.0,
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L3GD20_FULLSCALE_500 : 500.0,
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L3GD20_FULLSCALE_2000 : 2000.0,
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L3GD20_FULLSCALE_SELECTION: 2000.0}
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entry = self._conf[L3GD20_CTRL_REG4_ADDR] & L3GD20_FULLSCALE_SELECTION
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self._dpsFS= conv[entry]
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def convert_raw_to_dps(self, x):
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x = x[1]*256+x[0]
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if x & 0x8000:
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x = x - 65536
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return x * self._dpsFS / 1000.0
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def read_bytes(self, addr, nbytes):
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addr |= L3GD20_READWRITE_CMD
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if nbytes > 1:
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addr |= L3GD20_MULTIPLEBYTE_CMD
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self.cs_pin.low()
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self.spi.send(addr)
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if self.DEBUG:
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print("SPI read addr: ", addr)
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buf = self.spi.recv(nbytes)
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self.cs_pin.high()
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if self.DEBUG:
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print("SPI read data", buf)
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return buf
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def write_bytes(self, addr, buf):
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if len(buf) > 1:
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addr |= L3GD20_MULTIPLEBYTE_CMD
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self.cs_pin.low()
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self.spi.send(addr)
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if self.DEBUG:
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print("SPI write addr: ", addr)
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for b in buf:
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self.spi.send(b)
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if self.DEBUG:
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print("SPI write data: ", b)
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self.cs_pin.high()
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def read_id(self):
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return self.read_bytes(L3GD20_WHO_AM_I_ADDR, 1)[0]
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def x(self):
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return self.convert_raw_to_dps(self.read_bytes(L3GD20_OUT_X_L_ADDR, 2))
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def y(self):
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return self.convert_raw_to_dps(self.read_bytes(L3GD20_OUT_Y_L_ADDR, 2))
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def z(self):
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return self.convert_raw_to_dps(self.read_bytes(L3GD20_OUT_Z_L_ADDR, 2))
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def xyz(self):
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return (self.x(), self.y(), self.z())
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def temp(self):
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val = self.read_bytes(L3GD20_OUT_TEMP_ADDR, 1)[0]
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if val & 0x80:
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val -= 256
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return val

‎stmhal/boards/STM32F429DISC/mpconfigboard.h

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#define MICROPY_HW_ENABLE_SPI1 (0)
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#define MICROPY_HW_ENABLE_SPI2 (0)
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#define MICROPY_HW_ENABLE_SPI3 (0)
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#define MICROPY_HW_ENABLE_SPI4 (0)
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#define MICROPY_HW_ENABLE_SPI5 (1)
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#define MICROPY_HW_ENABLE_SPI6 (0)
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#define MICROPY_HW_ENABLE_CAN (1)
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// HSE is 8MHz

‎stmhal/dma.h

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#define DMA_STREAM_SPI1_RX DMA2_Stream2
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#define DMA_CHANNEL_SPI1_RX DMA_CHANNEL_3
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#define DMA_STREAM_SPI5_RX DMA2_Stream3
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#define DMA_CHANNEL_SPI5_RX DMA_CHANNEL_2
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#define DMA_STREAM_SDIO_RX DMA2_Stream3
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#define DMA_CHANNEL_SDIO_RX DMA_CHANNEL_4
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#define DMA_STREAM_SPI4_RX DMA2_Stream3
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#define DMA_CHANNEL_SPI4_RX DMA_CHANNEL_5
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#define DMA_STREAM_SPI5_TX DMA2_Stream4
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#define DMA_CHANNEL_SPI5_TX DMA_CHANNEL_2
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#define DMA_STREAM_SPI4_TX DMA2_Stream4
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#define DMA_CHANNEL_SPI4_TX DMA_CHANNEL_5
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#define DMA_STREAM_SPI6_TX DMA2_Stream5
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#define DMA_CHANNEL_SPI6_TX DMA_CHANNEL_1
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#define DMA_STREAM_SPI1_TX DMA2_Stream5
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#define DMA_CHANNEL_SPI1_TX DMA_CHANNEL_3
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#define DMA_STREAM_SPI6_RX DMA2_Stream6
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#define DMA_CHANNEL_SPI6_RX DMA_CHANNEL_1
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#define DMA_STREAM_SDIO_TX DMA2_Stream6
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#define DMA_CHANNEL_SDIO_TX DMA_CHANNEL_4
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