8000 stm32/network_lan.c: Allow defining phy_addr in the LAN constructor. · micropython/micropython@3e32374 · GitHub
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robert-hhrobert-hh
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stm32/network_lan.c: Allow defining phy_addr in the LAN constructor.
The default value is 0. Implementing that required changes to eth.c as well. The value of phy_addr is added to the eth_t data type. Tested with a STM32F767 and a STM32H750 device. Signed-off-by: robert-hh <robert@hammelrath.com>
1 parent 8fdcc25 commit 3e32374

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3 files changed

+32
-20
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+32
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lines changed

‎ports/stm32/eth.c

Original file line numberDiff line numberDiff line change
@@ -40,8 +40,7 @@
4040
#include "lwip/dhcp.h"
4141
#include "netif/ethernet.h"
4242

43-
// ETH PHY register definitions (for LAN8742)
44-
43+
// ETH PHY register definitions (for LAN8742 and LAN8720/LAN8710)
4544
#undef PHY_BCR
4645
#define PHY_BCR (0x0000)
4746
#define PHY_BCR_SOFT_RESET (0x8000)
@@ -137,6 +136,7 @@ typedef struct _eth_t {
137136
uint32_t trace_flags;
138137
struct netif netif;
139138
struct dhcp dhcp_struct;
139+
uint32_t phy_addr;
140140
} eth_t;
141141

142142
static eth_dma_t eth_dma __attribute__((aligned(16384)));
@@ -146,11 +146,13 @@ eth_t eth_instance;
146146
STATIC void eth_mac_deinit(eth_t *self);
147147
STATIC void eth_process_frame(eth_t *self, size_t len, const uint8_t *buf);
8000 148148

149-
STATIC void eth_phy_write(uint32_t reg, uint32_t val) {
149+
STATIC void eth_phy_write(uint32_t phy_addr, uint32_t reg, uint32_t val) {
150150
#if defined(STM32H5) || defined(STM32H7)
151151
while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
152152
}
153153
uint32_t ar = ETH->MACMDIOAR;
154+
ar &= ~ETH_MACMDIOAR_PA_Msk;
155+
ar |= (phy_addr << ETH_MACMDIOAR_PA_Pos);
154156
ar &= ~ETH_MACMDIOAR_RDA_Msk;
155157
ar |= reg << ETH_MACMDIOAR_RDA_Pos;
156158
ar &= ~ETH_MACMDIOAR_MOC_Msk;
@@ -165,18 +167,20 @@ STATIC void eth_phy_write(uint32_t reg, uint32_t val) {
165167
}
166168
ETH->MACMIIDR = val;
167169
uint32_t ar = ETH->MACMIIAR;
168-
ar = reg << ETH_MACMIIAR_MR_Pos | (ar & ETH_MACMIIAR_CR_Msk) | ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
170+
ar = (phy_addr << ETH_MACMIIAR_PA_Pos) | (reg << ETH_MACMIIAR_MR_Pos) | (ar & ETH_MACMIIAR_CR_Msk) | ETH_MACMIIAR_MW | ETH_MACMIIAR_MB;
169171
ETH->MACMIIAR = ar;
170172
while (ETH->MACMIIAR & ETH_MACMIIAR_MB) {
171173
}
172174
#endif
173175< 8000 div class="diff-text-inner">}
174176

175-
STATIC uint32_t eth_phy_read(uint32_t reg) {
177+
STATIC uint32_t eth_phy_read(uint32_t phy_addr, uint32_t reg) {
176178
#if defined(STM32H5) || defined(STM32H7)
177179
while (ETH->MACMDIOAR & ETH_MACMDIOAR_MB) {
178180
}
179181
uint32_t ar = ETH->MACMDIOAR;
182+
ar &= ~ETH_MACMDIOAR_PA_Msk;
183+
ar |= (phy_addr << ETH_MACMDIOAR_PA_Pos);
180184
ar &= ~ETH_MACMDIOAR_RDA_Msk;
181185
ar |= reg << ETH_MACMDIOAR_RDA_Pos;
182186
ar &= ~ETH_MACMDIOAR_MOC_Msk;
@@ -190,17 +194,18 @@ STATIC uint32_t eth_phy_read(uint32_t reg) {
190194
while (ETH->MACMIIAR & ETH_MACMIIAR_MB) {
191195
}
192196
uint32_t ar = ETH->MACMIIAR;
193-
ar = reg << ETH_MACMIIAR_MR_Pos | (ar & ETH_MACMIIAR_CR_Msk) | ETH_MACMIIAR_MB;
197+
ar = (phy_addr << ETH_MACMIIAR_PA_Pos) | (reg << ETH_MACMIIAR_MR_Pos) | (ar & ETH_MACMIIAR_CR_Msk) | ETH_MACMIIAR_MB;
194198
ETH->MACMIIAR = ar;
195199
while (ETH->MACMIIAR & ETH_MACMIIAR_MB) {
196200
}
197201
return ETH->MACMIIDR;
198202
#endif
199203
}
200204

201-
void eth_init(eth_t *self, int mac_idx) {
205+
void eth_init(eth_t *self, int mac_idx, uint32_t phy_addr, int phy_type) {
202206
mp_hal_get_mac(mac_idx, &self->netif.hwaddr[0]);
203207
self->netif.hwaddr_len = 6;
208+
self->phy_addr = phy_addr;
204209

205210
// Configure GPIO
206211
mp_hal_pin_config_alt_static(MICROPY_HW_ETH_MDC, MP_HAL_PIN_MODE_ALT, MP_HAL_PIN_PULL_NONE, STATIC_AF_ETH_MDC);
@@ -362,7 +367,7 @@ STATIC int eth_mac_init(eth_t *self) {
362367
#endif
363368

364369
// Reset the PHY
365-
eth_phy_write(PHY_BCR, PHY_BCR_SOFT_RESET);
370+
eth_phy_write(self->phy_addr, PHY_BCR, PHY_BCR_SOFT_RESET);
366371
mp_hal_delay_ms(50);
367372

368373
// Wait for the PHY link to be established
@@ -373,8 +378,8 @@ STATIC int eth_mac_init(eth_t *self) {
373378
eth_mac_deinit(self);
374379
return -MP_ETIMEDOUT;
375380
}
376-
uint16_t bcr = eth_phy_read(0);
377-
uint16_t bsr = eth_phy_read(1);
381+
uint16_t bcr = eth_phy_read(self->phy_addr, PHY_BCR);
382+
uint16_t bsr = eth_phy_read(self->phy_addr, PHY_BSR);
378383
switch (phy_state) {
379384
case 0:
380385
if (!(bcr & PHY_BCR_SOFT_RESET)) {
@@ -383,7 +388,7 @@ STATIC int eth_mac_init(eth_t *self) {
383388
break;
384389
case 1:
385390
if (bsr & PHY_BSR_LINK_STATUS) {
386-
eth_phy_write(PHY_BCR, PHY_BCR_AUTONEG_EN);
391+
eth_phy_write(self->phy_addr, PHY_BCR, PHY_BCR_AUTONEG_EN);
387392
phy_state = 2;
388393
}
389394
break;
@@ -398,7 +403,7 @@ STATIC int eth_mac_init(eth_t *self) {
398403
}
399404

400405
// Get register with link status
401-
uint16_t phy_scsr = eth_phy_read(PHY_SCSR);
406+
uint16_t phy_scsr = eth_phy_read(self->phy_addr, PHY_SCSR);
402407

403408
// Burst mode configuration
404409
#if defined(STM32H5) || defined(STM32H7)
@@ -845,7 +850,7 @@ int eth_link_status(eth_t *self) {
845850
return 2; // link no-ip;
846851
}
847852
} else {
848-
if (eth_phy_read(PHY_BSR) & PHY_BSR_LINK_STATUS) {
853+
if (eth_phy_read(self->phy_addr, PHY_BSR) & PHY_BSR_LINK_STATUS) {
849854
return 1; // link up
850855
} else {
851856
return 0; // link down
@@ -883,10 +888,10 @@ void eth_low_power_mode(eth_t *self, bool enable) {
883888
__HAL_RCC_ETH_CLK_ENABLE();
884889
#endif
885890

886-
uint16_t bcr = eth_phy_read(PHY_BCR);
891+
uint16_t bcr = eth_phy_read(self->phy_addr, PHY_BCR);
887892
if (enable) {
888893
// Enable low-power mode.
889-
eth_phy_write(PHY_BCR, bcr | PHY_BCR_POWER_DOWN);
894+
eth_phy_write(self->phy_addr, PHY_BCR, bcr | PHY_BCR_POWER_DOWN);
890895
// Disable eth clock.
891896
#if defined(STM32H7)
892897
__HAL_RCC_ETH1MAC_CLK_DISABLE();
@@ -895,7 +900,7 @@ void eth_low_power_mode(eth_t *self, bool enable) {
895900
#endif
896901
} else {
897902
// Disable low-power mode.
898-
eth_phy_write(PHY_BCR, bcr & (~PHY_BCR_POWER_DOWN));
903+
eth_phy_write(self->phy_addr, PHY_BCR, bcr & (~PHY_BCR_POWER_DOWN));
899904
}
900905
}
901906
#endif // defined(MICROPY_HW_ETH_MDC)
Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@
2929
typedef struct _eth_t eth_t;
3030
extern eth_t eth_instance;
3131

32-
void eth_init(eth_t *self, int mac_idx);
32+
void eth_init(eth_t *self, int mac_idx, uint32_t phy_addr, int phy_type);
3333
void eth_set_trace(eth_t *self, uint32_t value);
3434
struct netif *eth_netif(eth_t *self);
3535
int eth_link_status(eth_t *self);
Original file line numberDiff line numberDiff line change
@@ -53,10 +53,17 @@ STATIC void network_lan_print(const mp_print_t *print, mp_obj_t self_in, mp_prin
5353
);
5454
}
5555

56-
STATIC mp_obj_t network_lan_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) {
57-
mp_arg_check_num(n_args, n_kw, 0, 0, false);
56+
STATIC mp_obj_t network_lan_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) {
57+
enum { ARG_phy_addr};
58+
static const mp_arg_t allowed_args[] = {
59+
{ MP_QSTR_phy_addr, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} },
60+
};
61+
// Parse args.
62+
mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)];
63+
mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args);
64+
5865
const network_lan_obj_t *self = &network_lan_eth0;
59-
eth_init(self->eth, MP_HAL_MAC_ETH0);
66+
eth_init(self->eth, MP_HAL_MAC_ETH0, args[ARG_phy_addr].u_int);
6067
return MP_OBJ_FROM_PTR(self);
6168
}
6269