8000 py/emitnative: Improve Viper register-indexed code for Arm. · micropython/micropython@1d37caa · GitHub
[go: up one dir, main page]
Skip to content

Commit 1d37caa

Browse files
agattiagatti
committed
py/emitnative: Improve Viper register-indexed code for Arm.
This commit lets the Viper code generator use optimised code sequences for register-indexed load and store operations when generating Arm code. The existing code defaulted to generic multi-operations code sequences for Arm code on most cases. Now optimised implementations are provided for register-indexed loads and stores of all data sizes, taking at most two machine opcodes for each operation. Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
1 parent 186caf9 commit 1d37caa

File tree

3 files changed

+34
-2
lines changed

3 files changed

+34
-2
lines changed

‎py/asmarm.c

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -343,6 +343,12 @@ void asm_arm_ldrh_reg_reg(asm_arm_t *as, uint rd, uint rn) {
343343
emit_al(as, 0x1d000b0 | (rn << 16) | (rd << 12));
344344
}
345345

346+
void asm_arm_ldrh_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn) {
347+
// ldrh doesn't support scaled register index
348+
emit_al(as, 0x1a00080 | (ASM_ARM_REG_R8 << 12) | rn); // mov r8, rn, lsl #1
349+
emit_al(as, 0x19000b0 | (rm << 16) | (rd << 12) | ASM_ARM_REG_R8); // ldrh rd, [rm, r8];
350+
}
351+
346352
void asm_arm_ldrh_reg_reg_offset(asm_arm_t *as, uint rd, uint rn, uint byte_offset) {
347353
if (byte_offset < 0x100) {
348354
// ldrh rd, [rn, #off]
@@ -360,6 +366,16 @@ void asm_arm_ldrb_reg_reg(asm_arm_t *as, uint rd, uint rn) {
360366
emit_al(as, 0x5d00000 | (rn << 16) | (rd << 12));
361367
}
362368

369+
void asm_arm_ldrb_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn) {
370+
// ldrb rd, [rm, rn]
371+
emit_al(as, 0x7d00000 | (rm << 16) | (rd << 12) | rn);
372+
}
373+
374+
void asm_arm_ldr_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn) {
375+
// ldr rd, [rm, rn, lsl #2]
376+
emit_al(as, 0x7900100 | (rm << 16) | (rd << 12) | rn);
377+
}
378+
363379
void asm_arm_str_reg_reg(asm_arm_t *as, uint rd, uint rm, uint byte_offset) {
364380
// str rd, [rm, #off]
365381
emit_al(as, 0x5800000 | (rm << 16) | (rd << 12) | byte_offset);

‎py/asmarm.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,12 @@ void asm_arm_ldrb_reg_reg(asm_arm_t *as, uint rd, uint rn);
116116
void asm_arm_str_reg_reg(asm_arm_t *as, uint rd, uint rm, uint byte_offset);
117117
void asm_arm_strh_reg_reg(asm_arm_t *as, uint rd, uint rm);
118118
void asm_arm_strb_reg_reg(asm_arm_t *as, uint rd, uint rm);
119+
120+
// load from array
121+
void asm_arm_ldr_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);
122+
void asm_arm_ldrh_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);
123+
void asm_arm_ldrb_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);
124+
119125
// store to array
120126
void asm_arm_str_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);
121127
void asm_arm_strh_reg_reg_reg(asm_arm_t *as, uint rd, uint rm, uint rn);

‎py/emitnative.c

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1638,14 +1638,21 @@ static void emit_native_load_subscr(emit_t *emit) {
16381638
switch (vtype_base) {
16391639
case VTYPE_PTR8: {
16401640
// pointer to 8-bit memory
1641+
#if N_ARM
1642+
asm_arm_ldrb_reg_reg_reg(emit->as, REG_RET, REG_ARG_1, reg_index);
1643+
break;
1644+
#endif
16411645
// TODO optimise to use thumb ldrb r1, [r2, r3]
16421646
ASM_ADD_REG_REG(emit->as, REG_ARG_1, reg_index); // add index to base
16431647
ASM_LOAD8_REG_REG(emit->as, REG_RET, REG_ARG_1); // store value to (base+index)
16441648
break;
16451649
}
16461650
case VTYPE_PTR16: {
16471651
// pointer to 16-bit memory
1648-
#if N_XTENSA || N_XTENSAWIN
1652+
#if N_ARM
1653+
asm_arm_ldrh_reg_reg_reg(emit->as, REG_RET, REG_ARG_1, reg_index);
1654+
break;
1655+
#elif N_XTENSA || N_XTENSAWIN
16491656
asm_xtensa_op_addx2(emit->as, REG_ARG_1, reg_index, REG_ARG_1);
16501657
asm_xtensa_op_l16ui(emit->as, REG_RET, REG_ARG_1, 0);
16511658
break;
@@ -1657,7 +1664,10 @@ static void emit_native_load_subscr(emit_t *emit) {
16571664
}
16581665
case VTYPE_PTR32: {
16591666
// pointer to word-size memory
1660-
#if N_RV32
1667+
#if N_ARM
1668+
asm_arm_ldr_reg_reg_reg(emit->as, REG_RET, REG_ARG_1, reg_index);
1669+
break;
1670+
#elif N_RV32
16611671
asm_rv32_opcode_slli(emit->as, REG_TEMP2, reg_index, 2);
16621672
asm_rv32_opcode_cadd(emit->as, REG_ARG_1, REG_TEMP2);
16631673
asm_rv32_opcode_lw(emit->as, REG_RET, REG_ARG_1, 0);

0 commit comments

Comments
 (0)
0