8000 Commits · mahdizynali/verilog-digital-circuit-codes · GitHub

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Commits on Jun 9, 2023

Create arithmaticUnit.v
mahdizynali
authored
Create shiftLeftUnit.v
mahdizynali
authored
Create shiftRightUnit.v
mahdizynali
authored
Create mux4to1_8bit.v
mahdizynali
authored
Create mux4to1.v
mahdizynali
authored
Create mux2to1.v
mahdizynali
authored
Create logicUnit.v
mahdizynali
authored
Create fullAdder_8bit.v
mahdizynali
authored

Commits on Jun 6, 2023

Update fullAdder.v
mahdizynali
authored
Create fullAdder.v
mahdizynali
authored
Create fulladder.v
mahdizynali
authored
Create halfAdder.v
mahdizynali
authored

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