8000 [RISCV] Handle the pattern with swapped select operands · llvm/llvm-project@ee43e66 · GitHub
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[RISCV] Handle the pattern with swapped select operands
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3 files changed

+46
-25
lines changed

3 files changed

+46
-25
lines changed

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12080,10 +12080,15 @@ SDValue DAGCombiner::visitSELECT(SDNode *N) {
1208012080
return NewSel;
1208112081

1208212082
// (select (ugt x, C), (add x, ~C), x) -> (umin (add x, ~C), x)
12083+
// (select (ult x, C), x, (add x, -C)) -> (umin x, (add x, -C))
1208312084
APInt C;
12084-
if (CC == ISD::SETUGT && Cond0 == N2 && sd_match(Cond1, m_ConstInt(C)) &&
12085-
sd_match(N1, m_Add(m_Specific(N2), m_SpecificInt(~C))) && hasUMin(VT))
12086-
return DAG.getNode(ISD::UMIN, DL, VT, N1, N2);
12085+
if (sd_match(Cond1, m_ConstInt(C)) && hasUMin(VT)) {
12086+
if ((CC == ISD::SETUGT && Cond0 == N2 &&
12087+
sd_match(N1, m_Add(m_Specific(N2), m_SpecificInt(~C)))) ||
12088+
(CC == ISD::SETULT && Cond0 == N1 &&
12089+
sd_match(N2, m_Add(m_Specific(N1), m_SpecificInt(-C)))))
12090+
return DAG.getNode(ISD::UMIN, DL, VT, N1, N2);
12091+
}
1208712092
}
1208812093

1208912094
if (!VT.isVector())

‎llvm/test/CodeGen/RISCV/rv32zbb.ll

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1883,17 +1883,25 @@ define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {
18831883
}
18841884

18851885
define i32 @sub_if_uge_C_swapped_i32(i32 %x) {
1886-
; CHECK-LABEL: sub_if_uge_C_swapped_i32:
1887-
; CHECK: # %bb.0:
1888-
; CHECK-NEXT: lui a1, 16
1889-
; CHECK-NEXT: lui a2, 1048560
1890-
; CHECK-NEXT: addi a1, a1, -15
1891-
; CHECK-NEXT: sltu a1, a0, a1
1892-
; CHECK-NEXT: addi a1, a1, -1
1893-
; CHECK-NEXT: addi a2, a2, 15
1894-
; CHECK-NEXT: and a1, a1, a2
1895-
; CHECK-NEXT: add a0, a0, a1
1896-
; CHECK-NEXT: ret
1886+
; RV32I-LABEL: sub_if_uge_C_swapped_i32:
1887+
; RV32I: # %bb.0:
1888+
; RV32I-NEXT: lui a1, 16
1889+
; RV32I-NEXT: lui a2, 1048560
1890+
; RV32I-NEXT: addi a1, a1, -15
1891+
; RV32I-NEXT: sltu a1, a0, a1
1892+
; RV32I-NEXT: addi a1, a1, -1
1893+
; RV32I-NEXT: addi a2, a2, 15
1894+
; RV32I-NEXT: and a1, a1, a2
1895+
; RV32I-NEXT: add a0, a0, a1
1896+
; RV32I-NEXT: ret
1897+
;
1898+
; RV32ZBB-LABEL: sub_if_uge_C_swapped_i32:
1899+
; RV32ZBB: # %bb.0:
1900+
; RV32ZBB-NEXT: lui a1, 1048560
1901+
; RV32ZBB-NEXT: addi a1, a1, 15
1902+
; RV32ZBB-NEXT: add a1, a0, a1
1903+
; RV32ZBB-NEXT: minu a0, a0, a1
1904+
; RV32ZBB-NEXT: ret
18971905
%cmp = icmp ult i32 %x, 65521
18981906
%sub = add i32 %x, -65521
18991907
%cond = select i1 %cmp, i32 %x, i32 %sub

‎llvm/test/CodeGen/RISCV/rv64zbb.ll

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -2048,17 +2048,25 @@ define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) {
20482048
}
20492049

20502050
define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) {
2051-
; CHECK-LABEL: sub_if_uge_C_swapped_i32:
2052-
; CHECK: # %bb.0:
2053-
; CHECK-NEXT: lui a1, 16
2054-
; CHECK-NEXT: lui a2, 1048560
2055-
; CHECK-NEXT: addiw a1, a1, -15
2056-
; CHECK-NEXT: sltu a1, a0, a1
2057-
; CHECK-NEXT: addi a1, a1, -1
2058-
; CHECK-NEXT: addi a2, a2, 15
2059-
; CHECK-NEXT: and a1, a1, a2
2060-
; CHECK-NEXT: addw a0, a0, a1
2061-
; CHECK-NEXT: ret
2051+
; RV64I-LABEL: sub_if_uge_C_swapped_i32:
2052+
; RV64I: # %bb.0:
2053+
; RV64I-NEXT: lui a1, 16
2054+
; RV64I-NEXT: lui a2, 1048560
2055+
; RV64I-NEXT: addiw a1, a1, -15
2056+
; RV64I-NEXT: sltu a1, a0, a1
2057+
; RV64I-NEXT: addi a1, a1, -1
2058+
; RV64I-NEXT: addi a2, a2, 15
2059+
; RV64I-NEXT: and a1, a1, a2
2060+
; RV64I-NEXT: addw a0, a0, a1
2061+
; RV64I-NEXT: ret
2062+
;
2063+
; RV64ZBB-LABEL: sub_if_uge_C_swapped_i32:
2064+
; RV64ZBB: # %bb.0:
2065+
; RV64ZBB-NEXT: lui a1, 1048560
2066+
; RV64ZBB-NEXT: addi a1, a1, 15
2067+
; RV64ZBB-NEXT: addw a1, a0, a1
2068+
; RV64ZBB-NEXT: minu a0, a0, a1
2069+
; RV64ZBB-NEXT: ret
20622070
%cmp = icmp ult i32 %x, 65521
20632071
%sub = add i32 %x, -65521
20642072
%cond = select i1 %cmp, i32 %x, i32 %sub

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