8000 [RISCV][test] Add tests for subtraction if above threshold · llvm/llvm-project@e6e0f5f · GitHub
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[RISCV][test] Add tests for subtraction if above threshold
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‎llvm/test/CodeGen/RISCV/rv32zbb.ll

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Original file line numberDiff line numberDiff line change
@@ -1479,3 +1479,189 @@ entry:
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%cmp = icmp ne i32 %popcnt, 1
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ret i1 %cmp
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}
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define i8 @sub_if_uge_i8(i8 %x, i8 %y) {
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; CHECK-LABEL: sub_if_uge_i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: zext.b a2, a1
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; CHECK-NEXT: zext.b a3, a0
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; CHECK-NEXT: sltu a2, a3, a2
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; CHECK-NEXT: addi a2, a2, -1
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; CHECK-NEXT: and a1, a2, a1
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; CHECK-NEXT: sub a0, a0, a1
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; CHECK-NEXT: ret
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%cmp = icmp ult i8 %x, %y
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%select = select i1 %cmp, i8 0, i8 %y
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%sub = sub nuw i8 %x, %select
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ret i8 %sub
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}
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define i16 @sub_if_uge_i16(i16 %x, i16 %y) {
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; RV32I-LABEL: sub_if_uge_i16:
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; RV32I: # %bb.0:
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; RV32I-NEXT: lui a2, 16
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; RV32I-NEXT: addi a2, a2, -1
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; RV32I-NEXT: and a3, a1, a2
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; RV32I-NEXT: and a2, a0, a2
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; RV32I-NEXT: sltu a2, a2, a3
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; RV32I-NEXT: addi a2, a2, -1
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; RV32I-NEXT: and a1, a2, a1
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; RV32I-NEXT: sub a0, a0, a1
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; RV32I-NEXT: ret
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;
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; RV32ZBB-LABEL: sub_if_uge_i16:
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; RV32ZBB: # %bb.0:
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; RV32ZBB-NEXT: zext.h a2, a1
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; RV32ZBB-NEXT: zext.h a3, a0
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; RV32ZBB-NEXT: sltu a2, a3, a2
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; RV32ZBB-NEXT: addi a2, a2, -1
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; RV32ZBB-NEXT: and a1, a2, a1
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; RV32ZBB-NEXT: sub a0, a0, a1
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; RV32ZBB-NEXT: ret
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%cmp = icmp ult i16 %x, %y
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%select = select i1 %cmp, i16 0, i16 %y
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%sub = sub nuw i16 %x, %select
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ret i16 %sub
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}
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define i32 @sub_if_uge_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: sub_if_uge_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sltu a2, a0, a1
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; CHECK-NEXT: addi a2, a2, -1
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; CHECK-NEXT: and a1, a2, a1
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; CHECK-NEXT: sub a0, a0, a1
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; CHECK-NEXT: ret
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%cmp = icmp ult i32 %x, %y
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%select = select i1 %cmp, i32 0, i32 %y
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%sub = sub nuw 10000 i32 %x, %select
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ret i32 %sub
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}
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define i64 @sub_if_uge_i64(i64 %x, i64 %y) {
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; CHECK-LABEL: sub_if_uge_i64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: beq a1, a3, .LBB52_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: sltu a4, a1, a3
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; CHECK-NEXT: j .LBB52_3
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; CHECK-NEXT: .LBB52_2:
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; CHECK-NEXT: sltu a4, a0, a2
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; CHECK-NEXT: .LBB52_3:
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; CHECK-NEXT: addi a4, a4, -1
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; CHECK-NEXT: and a3, a4, a3
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; CHECK-NEXT: and a2, a4, a2
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; CHECK-NEXT: sltu a4, a0, a2
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; CHECK-NEXT: sub a1, a1, a3
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; CHECK-NEXT: sub a1, a1, a4
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; CHECK-NEXT: sub a0, a0, a2
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; CHECK-NEXT: ret
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%cmp = icmp ult i64 %x, %y
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%select = select i1 %cmp, i64 0, i64 %y
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%sub = sub nuw i64 %x, %select
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ret i64 %sub
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}
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define i128 @sub_if_uge_i128(i128 %x, i128 %y) {
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; CHECK-LABEL: sub_if_uge_i128:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lw a7, 4(a2)
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; CHECK-NEXT: lw a6, 8(a2)
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; CHECK-NEXT: lw t0, 12(a2)
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; CHECK-NEXT: lw a4, 12(a1)
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; CHECK-NEXT: lw a3, 4(a1)
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; CHECK-NEXT: lw a5, 8(a1)
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; CHECK-NEXT: beq a4, t0, .LBB53_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: sltu t1, a4, t0
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; CHECK-NEXT: j .LBB53_3
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; CHECK-NEXT: .LBB53_2:
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; CHECK-NEXT: sltu t1, a5, a6
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; CHECK-NEXT: .LBB53_3:
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; CHECK-NEXT: lw a2, 0(a2)
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; CHECK-NEXT: lw a1, 0(a1)
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; CHECK-NEXT: beq a3, a7, .LBB53_5
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; CHECK-NEXT: # %bb.4:
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; CHECK-NEXT: sltu t2, a3, a7
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; CHECK-NEXT: j .LBB53_6
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; CHECK-NEXT: .LBB53_5:
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; CHECK-NEXT: sltu t2, a1, a2
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; CHECK-NEXT: .LBB53_6:
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; CHECK-NEXT: xor t3, a4, t0
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; CHECK-NEXT: xor t4, a5, a6
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; CHECK-NEXT: or t3, t4, t3
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; CHECK-NEXT: beqz t3, .LBB53_8
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; CHECK-NEXT: # %bb.7:
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; CHECK-NEXT: mv t2, t1
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; CHECK-NEXT: .LBB53_8:
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; CHECK-NEXT: addi t2, t2, -1
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; CHECK-NEXT: and t1, t2, t0
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; CHECK-NEXT: and t0, t2, a2
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; CHECK-NEXT: and a7, t2, a7
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; CHECK-NEXT: sltu a2, a1, t0
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; CHECK-NEXT: and t2, t2, a6
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; CHECK-NEXT: mv a6, a2
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; CHECK-NEXT: beq a3, a7, .LBB53_10
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; CHECK-NEXT: # %bb.9:
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; CHECK-NEXT: sltu a6, a3, a7
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; CHECK-NEXT: .LBB53_10:
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; CHECK-NEXT: sub t3, a5, t2
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; CHECK-NEXT: sltu a5, a5, t2
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; CHECK-NEXT: sub a4, a4, t1
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; CHECK-NEXT: sub a3, a3, a7
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; CHECK-NEXT: sub a1, a1, t0
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; CHECK-NEXT: sltu a7, t3, a6
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; CHECK-NEXT: sub a4, a4, a5
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; CHECK-NEXT: sub a5, t3, a6
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; CHECK-NEXT: sub a3, a3, a2
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; CHECK-NEXT: sub a2, a4, a7
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; CHECK-NEXT: sw a1, 0(a0)
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; CHECK-NEXT: sw a3, 4(a0)
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; CHECK-NEXT: sw a5, 8(a0)
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; CHECK-NEXT: sw a2, 12(a0)
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; CHECK-NEXT: ret
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%cmp = icmp ult i128 %x, %y
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%select = select i1 %cmp, i128 0, i128 %y
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%sub = sub nuw i128 %x, %select
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ret i128 %sub
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}
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define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: sub_if_uge_multiuse_select_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sltu a2, a0, a1
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; CHECK-NEXT: addi a2, a2, -1
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; CHECK-NEXT: and a1, a2, a1
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; CHECK-NEXT: sub a0, a0, a1
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; CHECK-NEXT: sll a0, a0, a1
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; CHECK-NEXT: ret
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%cmp = icmp ult i32 %x, %y
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%select = select i1 %cmp, i32 0, i32 %y
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%sub = sub nuw i32 %x, %select
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%shl = shl i32 %sub, %select
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ret i32 %shl
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}
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define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) {
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; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sltu a2, a0, a1
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; CHECK-NEXT: addi a2, a2, -1
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; CHECK-NEXT: and a2, a2, a1
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; CHECK-NEXT: sub a2, a0, a2
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; CHECK-NEXT: bltu a0, a1, .LBB55_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: li a0, 4
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; CHECK-NEXT: sll a0, a2, a0
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB55_2:
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; CHECK-NEXT: li a0, 2
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; CHECK-NEXT: sll a0, a2, a0
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; CHECK-NEXT: ret
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%cmp = icmp ult i32 %x, %y
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%select = select i1 %cmp, i32 0, i32 %y
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%sub = sub nuw i32 %x, %select
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%select2 = select i1 %cmp, i32 2, i32 4
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%shl = shl i32 %sub, %select2
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ret i32 %shl
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}

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