E570 [X86] Add test cases to show missed rotate opportunities due to Simpl… · llvm/llvm-project@9ed890b · GitHub
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[X86] Add test cases to show missed rotate opportunities due to SimplifyDemandedBits.
llvm-svn: 332815
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‎llvm/test/CodeGen/X86/rotate4.ll‎

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@@ -281,3 +281,67 @@ define void @rotate_right_m16(i16* %p, i32 %amount) {
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ret void
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}
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define i32 @rotate_demanded_bits(i32, i32) {
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; CHECK-LABEL: rotate_demanded_bits:
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; CHECK: # %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: andl $30, %ecx
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll %cl, %eax
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; CHECK-NEXT: negl %ecx
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; CHECK-NEXT: andb $30, %cl
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; CHECK-NEXT: # kill: def $cl killed $cl killed $ecx
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; CHECK-NEXT: shrl %cl, %edi
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; CHECK-NEXT: orl %eax, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%3 = and i32 %1, 30
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%4 = shl i32 %0, %3
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%5 = sub nsw i32 0, %3
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%6 = and i32 %5, 30
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%7 = lshr i32 %0, %6
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%8 = or i32 %7, %4
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ret i32 %8
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}
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define i32 @rotate_demanded_bits_2(i32, i32) {
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; CHECK-LABEL: rotate_demanded_bits_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: andb $23, %sil
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: roll %cl, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%3 = and i32 %1, 23
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%4 = shl i32 %0, %3
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%5 = sub nsw i32 0, %3
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%6 = and i32 %5, 31
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%7 = lshr i32 %0, %6
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%8 = or i32 %7, %4
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ret i32 %8
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}
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define i32 @rotate_demanded_bits_3(i32, i32) {
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; CHECK-LABEL: rotate_demanded_bits_3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: addl %esi, %esi
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: andb $30, %cl
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: shll %cl, %eax
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; CHECK-NEXT: negl %esi
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; CHECK-NEXT: andb $30, %sil
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: shrl %cl, %edi
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; CHECK-NEXT: orl %eax, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%3 = shl i32 %1, 1
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%4 = and i32 %3, 30
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%5 = shl i32 %0, %4
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%6 = sub i32 0, %3
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%7 = and i32 %6, 30
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%8 = lshr i32 %0, %7
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%9 = or i32 %5, %8
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ret i32 %9
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}

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