From 705fe490c63b5781f543f3a9960d89068e6c2082 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Fri, 10 Nov 2023 11:45:25 -0800 Subject: [PATCH 1/2] Resolve HWDT Reset with core_esp8266_vm With the newer GCC compiler (after tag 3.0.2), example virtualmem was crashing with a HWDT reset. Reordered some SPI register set lines in spi_init(). New ordering was based on ::begin in SPI.cpp This change may resolve issues describe in https://github.com/esp8266/Arduino/discussions/9010 --- cores/esp8266/core_esp8266_vm.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cores/esp8266/core_esp8266_vm.cpp b/cores/esp8266/core_esp8266_vm.cpp index 3a63d65f7a..3631260021 100644 --- a/cores/esp8266/core_esp8266_vm.cpp +++ b/cores/esp8266/core_esp8266_vm.cpp @@ -168,13 +168,13 @@ static void spi_init(spi_regs *spi1) pinMode(miso, SPECIAL); pinMode(mosi, SPECIAL); pinMode(cs, SPECIAL); - spi1->spi_cmd = 0; + spi1->spi_ctrl = 0; // MSB first + plain SPI mode GPMUX &= ~(1 << 9); spi1->spi_clock = spi_clkval; - spi1->spi_ctrl = 0 ; // MSB first + plain SPI mode spi1->spi_ctrl1 = 0; // undocumented, clear for safety? spi1->spi_ctrl2 = 0; // No add'l delays on signals spi1->spi_user2 = 0; // No insn or insn_bits to set + spi1->spi_cmd = 0; } // Note: GCC optimization -O2 and -O3 tried and returned *slower* code than the default From ecf156eac37f574990aa4e122c77be55179bcdd0 Mon Sep 17 00:00:00 2001 From: M Hightower <27247790+mhightower83@users.noreply.github.com> Date: Sat, 11 Nov 2023 08:53:34 -0800 Subject: [PATCH 2/2] Added memory barrier to changes spi_ctrl appears to need setting before other SPI registers --- cores/esp8266/core_esp8266_vm.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cores/esp8266/core_esp8266_vm.cpp b/cores/esp8266/core_esp8266_vm.cpp index 3631260021..00f50e3981 100644 --- a/cores/esp8266/core_esp8266_vm.cpp +++ b/cores/esp8266/core_esp8266_vm.cpp @@ -161,14 +161,15 @@ static struct cache_line *__vm_cache; // Always points to MRU (hence the line be constexpr int addrmask = ~(sizeof(__vm_cache[0].w)-1); // Helper to mask off bits present in cache entry - static void spi_init(spi_regs *spi1) { pinMode(sck, SPECIAL); pinMode(miso, SPECIAL); pinMode(mosi, SPECIAL); pinMode(cs, SPECIAL); + // spi_ctrl appears to need setting before other SPI registers spi1->spi_ctrl = 0; // MSB first + plain SPI mode + asm("" ::: "memory"); GPMUX &= ~(1 << 9); spi1->spi_clock = spi_clkval; spi1->spi_ctrl1 = 0; // undocumented, clear for safety?