8000 qemu-arm: Merge RISC-V 32-bit support into qemu-arm port. · cuatrobits/micropython@0426934 · GitHub
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qemu-arm: Merge RISC-V 32-bit support into qemu-arm port.
Currently both the qemu-arm and qemu-riscv ports share a lot of code and functionality. This commit merges the qemu-riscv port into the qemu-arm port. The only real differences between the two are the toolchains used to build the code, and the initialisation/startup framework. Everything else is pretty much the same, so this brings the following benefits: - less code duplication - less burden on maintenance - generalised qemu port, could in the future support other architectures A new board `VIRT_RV32` has been added to the qemu-arm port which is the existing RISC-V board from the qemu-riscv port. To build it: $ make BOARD=VIRT_RV32 repl To cleanly separate the code for the different architectures, startup code has been moved to ports/qemu-arm/mcu/<arch>/. Signed-off-by: Damien George <damien@micropython.org>
1 parent f769b43 commit 0426934

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‎.github/workflows/ports_qemu-arm.yml

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@@ -19,14 +19,26 @@ concurrency:
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cancel-in-progress: true
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jobs:
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build_and_test:
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build_and_test_arm:
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- name: Install packages
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run: source tools/ci.sh && ci_qemu_arm_setup
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run: source tools/ci.sh && ci_qemu_setup_arm
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- name: Build and run test suite
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run: source tools/ci.sh && ci_qemu_arm_build
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run: source tools/ci.sh && ci_qemu_build_arm
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- name: Print failures
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if: failure()
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run: tests/run-tests.py --print-failures
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build_and_test_rv32:
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runs-on: ubuntu-latest
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steps:
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- uses: actions/checkout@v4
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- name: Install packages
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run: source tools/ci.sh && ci_qemu_setup_rv32
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- name: Build and run test suite
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run: source tools/ci.sh && ci_qemu_build_rv32
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- name: Print failures
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if: failure()
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run: tests/run-tests.py --print-failures

‎.github/workflows/ports_qemu-riscv.yml

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This file was deleted.

‎ports/qemu-arm/Makefile

Lines changed: 92 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,6 @@
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################################################################################
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# Initial setup of Makefile environment
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BOARD ?= MPS2_AN385
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# Make the build directory reflect the board.
@@ -14,16 +17,79 @@ QSTR_DEFS = qstrdefsport.h
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# MicroPython feature configurations
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MICROPY_ROM_TEXT_COMPR 10000 ESSION ?= 1
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ifeq ($(QEMU_ARCH),arm)
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FROZEN_MANIFEST ?= "freeze('test-frzmpy')"
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endif
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ifeq ($(QEMU_ARCH),riscv32)
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FROZEN_MANIFEST ?= "freeze('test-frzmpy', ('frozen_const.py', 'frozen_viper.py', 'native_frozen_align.py'))"
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endif
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# include py core make definitions
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include $(TOP)/py/py.mk
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include $(TOP)/extmod/extmod.mk
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################################################################################
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# ARM specific settings
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ifeq ($(QEMU_ARCH),arm)
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CROSS_COMPILE ?= arm-none-eabi-
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LDFLAGS += -nostdlib
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LIBS = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
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SRC_C += \
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mcu/arm/startup.c \
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shared/runtime/semihosting_arm.c \
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endif
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################################################################################
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# RISC-V 32-bit specific settings
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ifeq ($(QEMU_ARCH),riscv32)
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CROSS_COMPILE ?= riscv64-unknown-elf-
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GCC_VERSION = $(word 1, $(subst ., , $(shell $(CC) -dumpversion)))
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RV32_ABI = ilp32
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QEMU_ARGS += -bios none
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# GCC 10 and lower do not recognise the Zicsr extension in the architecture name.
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ifeq ($(shell test $(GCC_VERSION) -le 10; echo $$?),0)
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RV32_ARCH ?= rv32imac
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else
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# Recent GCC versions explicitly require to declare extensions.
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RV32_ARCH ?= rv32imac_zicsr
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endif
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AFLAGS += -mabi=$(RV32_ABI) -march=$(RV32_ARCH)
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CFLAGS += $(AFLAGS)
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LDFLAGS += -mabi=$(RV32_ABI) -march=$(RV32_ARCH) -Wl,-EL
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SRC_C += \
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mcu/rv32/interrupts.c \
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mcu/rv32/startup.c \
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SRC_BOARD_O += mcu/rv32/entrypoint.o
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endif
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################################################################################
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# Project specific settings and compiler/linker flags
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QEMU_SYSTEM = qemu-system-$(QEMU_ARCH)
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QEMU_ARGS += -machine $(QEMU_MACHINE) -nographic -monitor null -semihosting
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QEMU_ARGS += $(QEMU_EXTRA)
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# Specifying QEMU_DEBUG=1 will block qemu until a debugger is connected.
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ifeq ($(QEMU_DEBUG),1)
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QEMU_DEBUG_ARGS ?= -s
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QEMU_ARGS += -S $(QEMU_DEBUG_ARGS) $(QEMU_DEBUG_EXTRA)
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endif
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INC += -I.
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INC += -I$(TOP)
@@ -34,6 +100,8 @@ CFLAGS += $(INC) -Wall -Wpointer-arith -Wdouble-promotion -Wfloat-conversion -We
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-ffunction-sections -fdata-sections
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CFLAGS += $(CFLAGS_EXTRA)
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LDFLAGS += -T $(LDSCRIPT) -Wl,--gc-sections -Wl,-Map=$(@:.elf=.map)
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# Debugging/Optimization
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ifeq ($(DEBUG), 1)
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CFLAGS += -g
@@ -42,25 +110,31 @@ else
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COPT += -Os -DNDEBUG
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endif
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## With CoudeSourcery it's actually a little different, you just need `-T generic-m-hosted.ld`.
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## Although for some reason `$(LD)` will not find that linker script, it works with `$(CC)`.
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## It turns out that this is specific to CoudeSourcery, and ARM version of GCC ships something
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## else instead and according to the following files, this is what we need to pass to `$(CC).
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## - gcc-arm-none-eabi-4_8-2014q1/share/gcc-arm-none-eabi/samples/src/makefile.conf
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## - gcc-arm-none-eabi-4_8-2014q1/share/gcc-arm-none-eabi/samples/src/qemu/Makefile
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LDFLAGS= -T $(LDSCRIPT) --gc-sections -Map=$(@:.elf=.map)
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LIBS = $(shell $(CC) $(CFLAGS) -print-libgcc-file-name)
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# If Picolibc is available then select it explicitly. Ubuntu 22.04 ships its
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# bare metal RISC-V toolchain with Picolibc rather than Newlib, and the default
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# is "nosys" so a value must be provided. To avoid having per-distro
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# workarounds, always select Picolibc if available.
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PICOLIBC_SPECS = $(shell $(CC) --print-file-name=picolibc.specs)
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ifeq ($(PICOLIBC_SPECS),picolibc.specs)
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# Picolibc was not found.
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else
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$(info picolibc used $(PICOLIBC_SPECS))
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SPECS_FRAGMENT = --specs=$(PICOLIBC_SPECS)
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CFLAGS += $(SPECS_FRAGMENT)
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LDFLAGS += $(SPECS_FRAGMENT)
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endif
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SRC_C = \
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################################################################################
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# Source files and libraries
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SRC_C += \
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main.c \
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startup.c \
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uart.c \
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mphalport.c \
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shared/libc/string0.c \
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shared/readline/readline.c \
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shared/runtime/interrupt_char.c \
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shared/runtime/pyexec.c \
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shared/runtime/semihosting_arm.c \
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shared/runtime/stdout_helpers.c \
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shared/runtime/sys_stdio_mphal.c \
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@@ -75,6 +149,9 @@ OBJ += $(addprefix $(BUILD)/, $(LIB_SRC_C:.c=.o))
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# List of sources for qstr extraction
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SRC_QSTR += $(SRC_C) $(LIB_SRC_C)
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################################################################################
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# Main targets
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all: $(BUILD)/firmware.elf
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.PHONY: repl
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$(eval DIRNAME=ports/$(notdir $(CURDIR)))
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cd $(TOP)/tests && ./run-tests.py --target qemu-arm --device execpty:"$(QEMU_SYSTEM) $(QEMU_ARGS) -serial pty -kernel ../$(DIRNAME)/$<" $(RUN_TESTS_ARGS) $(RUN_TESTS_EXTRA)
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## `$(LD)` doesn't seem to like `--specs` for some reason, but we can just use `$(CC)` here.
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$(BUILD)/firmware.elf: $(LDSCRIPT) $(OBJ)
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$(Q)$(LD) $(LDFLAGS) -o $@ $(OBJ) $(LIBS)
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$(Q)$(CC) $(LDFLAGS) -o $@ $(OBJ) $(LIBS)
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$(Q)$(SIZE) $@
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################################################################################
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# Remaining make rules
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include $(TOP)/py/mkrules.mk

‎ports/qemu-arm/README.md

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MicroPython port to qemu-arm
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============================
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4-
This is experimental, community-supported port for Cortex-M emulation as
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provided by QEMU (http://qemu.org).
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This is experimental, community-supported port for Cortex-M and RISC-V RV32IMC
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emulation as provided by QEMU (http://qemu.org).
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The purposes of this port are to enable:
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@@ -18,6 +18,25 @@ The purposes of this port are to enable:
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- no need to use OpenOCD or anything else that might slow down the
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process in terms of plugging things together, pressing buttons, etc.
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Dependencies
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------------
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### ARM
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For ARM-based boards the build requires a bare-metal ARM toolchain, such as
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`arm-none-eabi-gcc`.
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### RISC-V
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For RISC-V-based boards the build requires a bare metal RISC-V toolchain with GCC 10
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or later, either with multilib support or 32 bits specific (M, C, and Zicsr
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extensions must be supported, along with ilp32 ABI). Both newlib and picolibc are
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supported, with the latter having precedence if found.
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Most pre-built toolchains should work out of the box, either coming from your
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Linux distribution's package manager, or independently packaged ones like
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[xPack](https://xpack.github.io/dev-tools/riscv-none-elf-gcc/).
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Build instructions
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------------------
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Available boards are:
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| Name for `BOARD=` | Corresponding qemu board |
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| ----------------- | ------------------------ |
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| `MICROBIT` | `microbit` |
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| `MPS2_AN385` | `mps2-an385` |
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| `NETDUINO2` | `netduino2` |
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| `SABRELITE` | `sabrelite` |
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| Name for `BOARD=` | Architecture | Corresponding qemu board |
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| ----------------- | ------------ | ------------------------ |
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| `MICROBIT` | `arm` | `microbit` |
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| `MPS2_AN385` | `arm` | `mps2-an385` |
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| `NETDUINO2` | `arm` | `netduino2` |
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| `SABRELITE` | `arm` | `sabrelite` |
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| `VIRT_RV32` | `riscv32` | `virt` |
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Running
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-------
@@ -84,3 +104,9 @@ The following options can be specified on the `make` command line:
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- `CFLAGS_EXTRA`: pass in extra flags for the compiler.
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- `RUN_TESTS_EXTRA`: pass in extra flags for `run-tests.py` when invoked via
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`make test`.
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- `QEMU_DEBUG=1`: when running qemu (via `repl`, `run` or `test` target), qemu
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will block until a debugger is connected. By default it waits for a gdb connection
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on TCP port 1234.
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- `QEMU_DEBUG_ARGS`: defaults to `-s` (gdb on TCP port 1234), but can be overridden
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with different qemu gdb arguments.
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- `QEMU_DEBUG_EXTRA`: extra options to pass to qemu when `QEMU_DEBUG=1` is used.

‎ports/qemu-arm/boards/MICROBIT.mk

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@@ -6,7 +6,7 @@ CFLAGS += -mthumb -mcpu=cortex-m0 -mfloat-abi=soft
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CFLAGS += -DQEMU_SOC_NRF51
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CFLAGS += -DMICROPY_HW_MCU_NAME='"nRF51"'
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LDSCRIPT = nrf51.ld
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LDSCRIPT = mcu/arm/nrf51.ld
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SRC_BOARD_O = shared/runtime/gchelper_native.o shared/runtime/gchelper_thumb1.o
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‎ports/qemu-arm/boards/MPS2_AN385.mk

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CFLAGS += -DQEMU_SOC_MPS2
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CFLAGS += -DMICROPY_HW_MCU_NAME='"Cortex-M3"'
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LDSCRIPT = mps2.ld
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LDSCRIPT = mcu/arm/mps2.ld
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SRC_BOARD_O = shared/runtime/gchelper_native.o shared/runtime/gchelper_thumb2.o
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‎ports/qemu-arm/boards/NETDUINO2.mk

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CFLAGS += -DQEMU_SOC_STM32
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CFLAGS += -DMICROPY_HW_MCU_NAME='"STM32"'
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LDSCRIPT = stm32.ld
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LDSCRIPT = mcu/arm/stm32.ld
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SRC_BOARD_O = shared/runtime/gchelper_native.o shared/runtime/gchelper_thumb2.o
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‎ports/qemu-arm/boards/SABRELITE.mk

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# Cortex-A9 should support unaligned-access, but qemu doesn't seem to.
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CFLAGS += -mno-unaligned-access
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LDSCRIPT = imx6.ld
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LDSCRIPT = mcu/arm/imx6.ld
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SRC_BOARD_O = shared/runtime/gchelper_generic.o
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‎ports/qemu-arm/boards/VIRT_RV32.mk

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QEMU_ARCH = riscv32
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QEMU_MACHINE = virt
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CFLAGS += -DQEMU_SOC_VIRT
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CFLAGS += -DMICROPY_HW_MCU_NAME='"$(RV32_ARCH)"'
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LDSCRIPT = mcu/rv32/virt.ld
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SRC_BOARD_O += shared/runtime/gchelper_native.o shared/runtime/gchelper_rv32i.o
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MPY_CROSS_FLAGS += -march=rv32imc
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# These Thumb tests don't run on RV32, so exclude them.
14+
RUN_TESTS_ARGS = --exclude 'inlineasm|qemu-arm/asm_test'

‎ports/qemu-arm/imx6.ld renamed to ‎ports/qemu-arm/mcu/arm/imx6.ld

File renamed without changes.

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