8000 Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm · codeguru85/linux@e3ff911 · GitHub
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torvaldstorvalds
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Merge branch 'fixes' of git://git.linaro.org/people/rmk/linux-arm
Pull ARM fixes from Russell King: "Another round of ARM fixes. Largest one is the second half of the PJ4B fix which was pushed in the previous -rc - this one was delayed because its original caused a build regression while trying to fix a regression! As ever, noMMU gets forgotten when fixing problems on MMU, so we have a noMMU fix for a previous fix included in this set. A couple of fixes from Lorenzo for problems with the ARM DT CPU code, and a one liner to remove the buggy 'wait for interrupt' with FA526 cores" * 'fixes' of git://git.linaro.org/people/rmk/linux-arm: ARM: 7773/1: PJ4B: Add support for errata 4742 ARM: 7772/1: Fix missing flush_kernel_dcache_page() for noMMU ARM: 7763/1: kernel: fix __cpu_logical_map default initialization ARM: 7762/1: kernel: fix arm_dt_init_cpu_maps() to skip non-cpu nodes ARM: 7760/1: cpu_fa526_do_idle: remove WFI
2 parents de6e131 + 3e0a07f commit e3ff911

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‎arch/arm/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -1087,6 +1087,20 @@ if !MMU
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source "arch/arm/Kconfig-nommu"
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endif
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1090+
config PJ4B_ERRATA_4742
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bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
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depends on CPU_PJ4B && MACH_ARMADA_370
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default y
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help
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When coming out of either a Wait for Interrupt (WFI) or a Wait for
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Event (WFE) IDLE states, a specific timing sensitivity exists between
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the retiring WFI/WFE instructions and the newly issued subsequent
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instructions. This sensitivity can result in a CPU hang scenario.
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Workaround:
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The software must insert either a Data Synchronization Barrier (DSB)
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or Data Memory Barrier (DMB) command immediately after the WFI/WFE
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instruction
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config ARM_ERRATA_326103
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bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
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depends on CPU_V6

‎arch/arm/include/asm/cputype.h

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@@ -32,6 +32,8 @@
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#define MPIDR_HWID_BITMASK 0xFFFFFF
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#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
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#define MPIDR_LEVEL_BITS 8
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#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
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‎arch/arm/include/asm/glue-proc.h

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@@ -230,6 +230,15 @@
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# endif
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#endif
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233+
#ifdef CONFIG_CPU_PJ4B
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# ifdef CPU_NAME
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# undef MULTI_CPU
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# define MULTI_CPU
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# else
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# define CPU_NAME cpu_pj4b
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# endif
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#endif
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#ifndef MULTI_CPU
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#define cpu_proc_init __glue(CPU_NAME,_proc_init)
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#define cpu_proc_fin __glue(CPU_NAME,_proc_fin)

‎arch/arm/include/asm/smp_plat.h

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Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@ static inline int cache_ops_need_broadcast(void)
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/*
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* Logical CPU mapping.
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*/
52-
extern int __cpu_logical_map[];
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extern u32 __cpu_logical_map[];
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#define cpu_logical_map(cpu) __cpu_logical_map[cpu]
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/*
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* Retrieve logical cpu index corresponding to a given MPIDR[23:0]

‎arch/arm/kernel/devtree.c

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,7 @@ void __init arm_dt_init_cpu_maps(void)
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u32 i, j, cpuidx = 1;
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u32 mpidr = is_smp() ? read_cpuid_mpidr() & MPIDR_HWID_BITMASK : 0;
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85-
u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = UINT_MAX };
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u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
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bool bootcpu_valid = false;
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cpus = of_find_node_by_path("/cpus");
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@@ -92,6 +92,9 @@ void __init arm_dt_init_cpu_maps(void)
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for_each_child_of_node(cpus, cpu) {
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u32 hwid;
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95+
if (of_node_cmp(cpu->type, "cpu"))
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continue;
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pr_debug(" * %s...\n", cpu->full_name);
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/*
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* A device tree containing CPU nodes with missing "reg"

‎arch/arm/kernel/setup.c

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Original file line numberDiff line numberDiff line change
@@ -444,7 +444,7 @@ void notrace cpu_init(void)
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: "r14");
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}
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447-
int __cpu_logical_map[NR_CPUS];
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u32 __cpu_logical_map[NR_CPUS] = { [0 ... NR_CPUS-1] = MPIDR_INVALID };
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void __init smp_setup_processor_id(void)
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{

‎arch/arm/mm/nommu.c

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Original file line numberDiff line numberDiff line change
@@ -57,6 +57,12 @@ void flush_dcache_page(struct page *page)
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}
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EXPORT_SYMBOL(flush_dcache_page);
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60+
void flush_kernel_dcache_page(struct page *page)
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{
62+
__cpuc_flush_dcache_area(page_address(page), PAGE_SIZE);
63+
}
64+
EXPORT_SYMBOL(flush_kernel_dcache_page);
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void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
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unsigned long uaddr, void *dst, const void *src,
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unsigned long len)

‎arch/arm/mm/proc-fa526.S

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Original file line numberDiff line numberDiff line change
@@ -81,7 +81,6 @@ ENDPROC(cpu_fa526_reset)
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*/
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.align 4
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ENTRY(cpu_fa526_do_idle)
84-
mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
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mov pc, lr
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‎arch/arm/mm/proc-macros.S

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Original file line numberDiff line numberDiff line change
@@ -333,3 +333,8 @@ ENTRY(\name\()_tlb_fns)
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.endif
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.size \name\()_tlb_fns, . - \name\()_tlb_fns
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.endm
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.macro globl_equ x, y
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.globl \x
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.equ \x, \y
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.endm

‎arch/arm/mm/proc-v7.S

Lines changed: 31 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,29 @@ ENTRY(cpu_v7_do_resume)
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mov r0, r8 @ control register
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b cpu_resume_mmu
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ENDPROC(cpu_v7_do_resume)
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#endif
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#ifdef CONFIG_CPU_PJ4B
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globl_equ cpu_pj4b_switch_mm, cpu_v7_switch_mm
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globl_equ cpu_pj4b_set_pte_ext, cpu_v7_set_pte_ext
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globl_equ cpu_pj4b_proc_init, cpu_v7_proc_init
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globl_equ cpu_pj4b_proc_fin, cpu_v7_proc_fin
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globl_equ cpu_pj4b_reset, cpu_v7_reset
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#ifdef CONFIG_PJ4B_ERRATA_4742
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ENTRY(cpu_pj4b_do_idle)
151+
dsb @ WFI may enter a low-power mode
152+
wfi
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dsb @barrier
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mov pc, lr
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ENDPROC(cpu_pj4b_do_idle)
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#else
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globl_equ cpu_pj4b_do_idle, cpu_v7_do_idle
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#endif
159+
globl_equ cpu_pj4b_dcache_clean_area, cpu_v7_dcache_clean_area
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globl_equ cpu_pj4b_do_suspend, cpu_v7_do_suspend
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globl_equ cpu_pj4b_do_resume, cpu_v7_do_resume
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globl_equ cpu_pj4b_suspend_size, cpu_v7_suspend_size
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141164
#endif
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143166
__CPUINIT
@@ -350,6 +373,9 @@ __v7_setup_stack:
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351374
@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
352375
define_processor_functions v7, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
376+
#ifdef CONFIG_CPU_PJ4B
377+
define_processor_functions pj4b, dabort=v7_early_abort, pabort=v7_pabort, suspend=1
378+
#endif
353379

354380
.section ".rodata"
355381

@@ -362,7 +388,7 @@ __v7_setup_stack:
362388
/*
363389
* Standard v7 proc info content
364390
*/
365-
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0
391+
.macro __v7_proc initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
366392
ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
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PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
368394
ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
@@ -375,7 +401,7 @@ __v7_setup_stack:
375401
.long HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB | HWCAP_FAST_MULT | \
376402
HWCAP_EDSP | HWCAP_TLS | \hwcaps
377403
.long cpu_v7_name
378-
.long v7_processor_functions
404+
.long \proc_fns
379405
.long v7wbi_tlb_fns
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.long v6_user_fns
381407
.long v7_cache_fns
@@ -407,12 +433,14 @@ __v7_ca9mp_proc_info:
407433
/*
408434
* Marvell PJ4B processor.
409435
*/
436+
#ifdef CONFIG_CPU_PJ4B
410437
.type __v7_pj4b_proc_info, #object
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__v7_pj4b_proc_info:
412439
.long 0x560f5800
413440
.long 0xff0fff00
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__v7_proc __v7_pj4b_setup
441+
__v7_proc __v7_pj4b_setup, proc_fns = pj4b_processor_functions
415442
.size __v7_pj4b_proc_info, . - __v7_pj4b_proc_info
443+
#endif
416444

417445
/*
418446
* ARM Ltd. Cortex A7 processor.

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