8000 fix for peripheral clock read on stm32h7 · carlossless/circuitpython@330480d · GitHub
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fix for peripheral clock read on stm32h7
1 parent e3c4aeb commit 330480d
8000

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‎ports/stm/peripherals/timers.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -164,7 +164,7 @@ uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef *timer) {
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source = HAL_RCC_GetPCLK2Freq();
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// 0b0xx means not divided; 0b100 is divide by 2; 0b101 by 4; 0b110 by 8; 0b111 by 16.
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#ifdef STM32H7
167-
clk_div = (RCC->CFGR & RCC_D2CFGR_D2PPRE2);
167+
clk_div = (RCC->D2CFGR & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos;
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#else
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clk_div = (RCC->CFGR & RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos;
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#endif
@@ -173,7 +173,7 @@ uint32_t stm_peripherals_timer_get_source_freq(TIM_TypeDef *timer) {
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source = HAL_RCC_GetPCLK1Freq();
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// 0b0xx means not divided; 0b100 is divide by 2; 0b101 by 4; 0b110 by 8; 0b111 by 16.
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#ifdef STM32H7
176-
clk_div = (RCC->CFGR & RCC_D1CFGR_D1PPRE_Msk);
176+
clk_div = (RCC->D1CFGR & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos;
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#else
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clk_div = (RCC->CFGR & RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos;
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#endif

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