8000 drm/i915: vlv: add runtime PM support · bsd-unix/linux@ddeea5b · GitHub
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drm/i915: vlv: add runtime PM support
Add runtime PM support for VLV, but leave it disabled. The next patch enables it. The suspend/resume sequence used is based on [1] and [2]. In practice we depend on the GT RC6 mechanism to save the HW context depending on the render and media power wells. By the time we run the runtime suspend callback the display side is also off and the HW context for that is managed by the display power domain framework. Besides the above there are Gunit registers that depend on a system-wide power well. This power well goes off once the device enters any of the S0i[R123] states. To handle this scenario, save/restore these Gunit registers. Note that this is not the complete register set dictated by [2], to remove some overhead, registers that are known not to be used are ignored. Also some registers are fully setup by initialization functions called during resume, these are not saved either. The list of registers can be further reduced, see the TODO note in the code. [1] VLV_gfx_clocking_PM_reset_y12w21d3 / "Driver D3 entry/exit" [2] VLV2_S0IXRegs v2: - unchanged v3: - fix s/GEN6_PMIIR/GEN6_PMIMR/ typo when saving/restoring registers (Ville) v4: - rebased on the previous patch fixing GEN register prefixes Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> [ rebased (according to v4) ] Signed-off-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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‎drivers/gpu/drm/i915/i915_drv.c

Lines changed: 327 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -939,6 +939,198 @@ static int hsw_runtime_resume(struct drm_i915_private *dev_priv)
939939
return 0;
940940
}
941941

942+
/*
943+
* Save all Gunit registers that may be lost after a D3 and a subsequent
944+
* S0i[R123] transition. The list of registers needing a save/restore is
945+
* defined in the VLV2_S0IXRegs document. This documents marks all Gunit
946+
* registers in the following way:
947+
* - Driver: saved/restored by the driver
948+
* - Punit : saved/restored by the Punit firmware
949+
* - No, w/o marking: no need to save/restore, since the register is R/O or
950+
* used internally by the HW in a way that doesn't depend
951+
* keeping the content across a suspend/resume.
952+
* - Debug : used for debugging
953+
*
954+
* We save/restore all registers marked with 'Driver', with the following
955+
* exceptions:
956+
* - Registers out of use, including also registers marked with 'Debug'.
957+
* These have no effect on the driver's operation, so we don't save/restore
958+
* them to reduce the overhead.
959+
* - Registers that are fully setup by an initialization function called from
960+
* the resume path. For example many clock gating and RPS/RC6 registers.
961+
* - Registers that provide the right functionality with their reset defaults.
962+
*
963+
* TODO: Except for registers that based on the above 3 criteria can be safely
964+
* ignored, we save/restore all others, practically treating the HW context as
965+
* a black-box for the driver. Further investigation is needed to reduce the
966+
* saved/restored registers even further, by following the same 3 criteria.
967+
*/
968+
static void vlv_save_gunit_s0ix_state(struct drm_i915_private *dev_priv)
969+
{
970+
struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
971+
int i;
972+
973+
/* GAM 0x4000-0x4770 */
974+
s->wr_watermark = I915_READ(GEN7_WR_WATERMARK);
975+
s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL);
976+
s->arb_mode = I915_READ(ARB_MODE);
977+
s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0);
978+
s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1);
979+
980+
for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
981+
s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS_BASE + i * 4);
982+
983+
s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
984+
s->gfx_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT);
985+
986+
s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7);
987+
s->ecochk = I915_READ(GAM_ECOCHK);
988+
s->bsd_hwsp = I915_READ(BSD_HWS_PGA_GEN7);
989+
s->blt_hwsp = I915_READ(BLT_HWS_PGA_GEN7);
990+
991+
s->tlb_rd_addr = I915_READ(GEN7_TLB_RD_ADDR);
992+
993+
/* MBC 0x9024-0x91D0, 0x8500 */
994+
s->g3dctl = I915_READ(VLV_G3DCTL);
995+
s->gsckgctl = I915_READ(VLV_GSCKGCTL);
996+
s->mbctl = I915_READ(GEN6_MBCTL);
997+
998+
/* GCP 0x9400-0x9424, 0x8100-0x810C */
999+
s->ucgctl1 = I915_READ(GEN6_UCGCTL1);
1000+
s->ucgctl3 = I915_READ(GEN6_UCGCTL3);
1001+
s->rcgctl1 = I915_READ(GEN6_RCGCTL1);
1002+
s->rcgctl2 = I915_READ(GEN6_RCGCTL2);
1003+
s->rstctl = I915_READ(GEN6_RSTCTL);
1004+
s->misccpctl = I915_READ(GEN7_MISCCPCTL);
1005+
1006+
/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1007+
s->gfxpause = I915_READ(GEN6_GFXPAUSE);
1008+
s->rpdeuhwtc = I915_READ(GEN6_RPDEUHWTC);
1009+
s->rpdeuc = I915_READ(GEN6_RPDEUC);
1010+
s->ecobus = I915_READ(ECOBUS);
1011+
s->pwrdwnupctl = I915_READ(VLV_PWRDWNUPCTL);
1012+
s->rp_down_timeout = I915_READ(GEN6_RP_DOWN_TIMEOUT);
1013+
s->rp_deucsw = I915_READ(GEN6_RPDEUCSW);
1014+
s->rcubmabdtmr = I915_READ(GEN6_RCUBMABDTMR);
1015+
s->rcedata = I915_READ(VLV_RCEDATA);
1016+
s->spare2gh = I915_READ(VLV_SPAREG2H);
1017+
1018+
/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1019+
s->gt_imr = I915_READ(GTIMR);
1020+
s->gt_ier = I915_READ(GTIER);
1021+
s->pm_imr = I915_READ(GEN6_PMIMR);
1022+
s->pm_ier = I915_READ(GEN6_PMIER);
1023+
1024+
for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1025+
s->gt_scratch[i] = I915_READ(GEN7_GT_SCRATCH_BASE + i * 4);
1026+
1027+
/* GT SA CZ domain, 0x100000-0x138124 */
1028+
s->tilectl = I915_READ(TILECTL);
1029+
s->gt_fifoctl = I915_READ(GTFIFOCTL);
1030+
s->gtlc_wake_ctrl = I915_READ(VLV_GTLC_WAKE_CTRL);
1031+
s->gtlc_survive = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1032+
s->pmwgicz = I915_READ(VLV_PMWGICZ);
1033+
1034+
/* Gunit-Display CZ domain, 0x182028-0x1821CF */
1035+
s->gu_ctl0 = I915_READ(VLV_GU_CTL0);
1036+
s->gu_ctl1 = I915_READ(VLV_GU_CTL1);
1037+
s->clock_gate_dis2 = I915_READ(VLV_GUNIT_CLOCK_GATE2);
1038+
1039+
/*
1040+
* Not saving any of:
1041+
* DFT, 0x9800-0x9EC0
1042+
* SARB, 0xB000-0xB1FC
1043+
* GAC, 0x5208-0x524C, 0x14000-0x14C000
1044+
* PCI CFG
1045+
*/
1046+
}
1047+
1048+
static void vlv_restore_gunit_s0ix_state(struct drm_i915_private *dev_priv)
1049+
{
1050+
struct vlv_s0ix_state *s = &dev_priv->vlv_s0ix_state;
1051+
u32 val;
1052+
int i;
1053+
1054+
/* GAM 0x4000-0x4770 */
1055+
I915_WRITE(GEN7_WR_WATERMARK, s->wr_watermark);
1056+
I915_WRITE(GEN7_GFX_PRIO_CTRL, s->gfx_prio_ctrl);
1057+
I915_WRITE(ARB_MODE, s->arb_mode | (0xffff << 16));
1058+
I915_WRITE(GEN7_GFX_PEND_TLB0, s->gfx_pend_tlb0);
1059+
I915_WRITE(GEN7_GFX_PEND_TLB1, s->gfx_pend_tlb1);
1060+
1061+
for (i = 0; i < ARRAY_SIZE(s->lra_limits); i++)
1062+
I915_WRITE(GEN7_LRA_LIMITS_BASE + i * 4, s->lra_limits[i]);
1063+
1064+
I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->media_max_req_count);
1065+
I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT, s->gfx_max_req_count);
1066+
1067+
I915_WRITE(RENDER_HWS_PGA_GEN7, s->render_hwsp);
1068+
I915_WRITE(GAM_ECOCHK, s->ecochk);
1069+
I915_WRITE(BSD_HWS_PGA_GEN7, s->bsd_hwsp);
1070+
I915_WRITE(BLT_HWS_PGA_GEN7, s->blt_hwsp);
1071+
1072+
I915_WRITE(GEN7_TLB_RD_ADDR, s->tlb_rd_addr);
1073+
1074+
/* MBC 0x9024-0x91D0, 0x8500 */
1075+
I915_WRITE(VLV_G3DCTL, s->g3dctl);
1076+
I915_WRITE(VLV_GSCKGCTL, s->gsckgctl);
1077+
I915_WRITE(GEN6_MBCTL, s->mbctl);
1078+
1079+
/* GCP 0x9400-0x9424, 0x8100-0x810C */
1080+
I915_WRITE(GEN6_UCGCTL1, s->ucgctl1);
1081+
I915_WRITE(GEN6_UCGCTL3, s->ucgctl3);
1082+
I915_WRITE(GEN6_RCGCTL1, s->rcgctl1);
1083+
I915_WRITE(GEN6_RCGCTL2, s->rcgctl2);
1084+
I915_WRITE(GEN6_RSTCTL, s->rstctl);
1085+
I915_WRITE(GEN7_MISCCPCTL, s->misccpctl);
1086+
1087+
/* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1088+
I915_WRITE(GEN6_GFXPAUSE, s->gfxpause);
1089+
I915_WRITE(GEN6_RPDEUHWTC, s->rpdeuhwtc);
1090+
I915_WRITE(GEN6_RPDEUC, s->rpdeuc);
1091+
I915_WRITE(ECOBUS, s->ecobus);
1092+
I915_WRITE(VLV_PWRDWNUPCTL, s->pwrdwnupctl);
1093+
I915_WRITE(GEN6_RP_DOWN_TIMEOUT,s->rp_down_timeout);
1094+
I915_WRITE(GEN6_RPDEUCSW, s->rp_deucsw);
1095+
I915_WRITE(GEN6_RCUBMABDTMR, s->rcubmabdtmr);
1096+
I915_WRITE(VLV_RCEDATA, s->rcedata);
1097+
I915_WRITE(VLV_SPAREG2H, s->spare2gh);
1098+
1099+
/* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1100+
I915_WRITE(GTIMR, s->gt_imr);
1101+
I915_WRITE(GTIER, s->gt_ier);
1102+
I915_WRITE(GEN6_PMIMR, s->pm_imr);
1103+
I915_WRITE(GEN6_PMIER, s->pm_ier);
1104+
1105+
for (i = 0; i < ARRAY_SIZE(s->gt_scratch); i++)
1106+
I915_WRITE(GEN7_GT_SCRATCH_BASE + i * 4, s->gt_scratch[i]);
1107+
1108+
/* GT SA CZ domain, 0x100000-0x138124 */
1109+
I915_WRITE(TILECTL, s->tilectl);
1110+
I915_WRITE(GTFIFOCTL, s->gt_fifoctl);
1111+
/*
1112+
* Preserve the GT allow wake and GFX force clock bit, they are not
1113+
* be restored, as they are used to control the s0ix suspend/resume
1114+
* sequence by the caller.
1115+
*/
1116+
val = I915_READ(VLV_GTLC_WAKE_CTRL);
1117+
val &= VLV_GTLC_ALLOWWAKEREQ;
1118+
val |= s->gtlc_wake_ctrl & ~VLV_GTLC_ALLOWWAKEREQ;
1119+
I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1120+
1121+
val = I915_READ(VLV_GTLC_SURVIVABILITY_REG);
1122+
val &= VLV_GFX_CLK_FORCE_ON_BIT;
1123+
val |= s->gtlc_survive & ~VLV_GFX_CLK_FORCE_ON_BIT;
1124+
I915_WRITE(VLV_GTLC_SURVIVABILITY_REG, val);
1125+
1126+
I915_WRITE(VLV_PMWGICZ, s->pmwgicz);
1127+
1128+
/* Gunit-Display CZ domain, 0x182028-0x1821CF */
1129+
I915_WRITE(VLV_GU_CTL0, s->gu_ctl0);
1130+
I915_WRITE(VLV_GU_CTL1, s->gu_ctl1);
1131+
I915_WRITE(VLV_GUNIT_CLOCK_GATE2, s->clock_gate_dis2);
1132+
}
1133+
9421134
int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
9431135
{
9441136
u32 val;
@@ -976,6 +1168,137 @@ int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool force_on)
9761168
#undef COND
9771169
}
9781170

1171+
static int vlv_allow_gt_wake(struct drm_i915_private *dev_priv, bool allow)
1172+
{
1173+
u32 val;
1174+
int err = 0;
1175+
1176+
val = I915_READ(VLV_GTLC_WAKE_CTRL);
1177+
val &= ~VLV_GTLC_ALLOWWAKEREQ;
1178+
if (allow)
1179+
val |= VLV_GTLC_ALLOWWAKEREQ;
1180+
I915_WRITE(VLV_GTLC_WAKE_CTRL, val);
1181+
POSTING_READ(VLV_GTLC_WAKE_CTRL);
1182+
1183+
#define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1184+
allow)
1185+
err = wait_for(COND, 1);
1186+
if (err)
1187+
DRM_ERROR("timeout disabling GT waking\n");
1188+
return err;
1189+
#undef COND
1190+
}
1191+
1192+
static int vlv_wait_for_gt_wells(struct drm_i915_private *dev_priv,
1193+
bool wait_for_on)
1194+
{
1195+
u32 mask;
1196+
u32 val;
1197+
int err;
1198+
1199+
mask = VLV_GTLC_PW_MEDIA_STATUS_MASK | VLV_GTLC_PW_RENDER_STATUS_MASK;
1200+
val = wait_for_on ? mask : 0;
1201+
#define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1202+
if (COND)
1203+
return 0;
1204+
1205+
DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1206+
wait_for_on ? "on" : "off",
1207+
I915_READ(VLV_GTLC_PW_STATUS));
1208+
1209+
/*
1210+
* RC6 transitioning can be delayed up to 2 msec (see
1211+
* valleyview_enable_rps), use 3 msec for safety.
1212+
*/
1213+
err = wait_for(COND, 3);
1214+
if (err)
1215+
DRM_ERROR("timeout waiting for GT wells to go %s\n",
1216+
wait_for_on ? "on" : "off");
1217+
1218+
return err;
1219+
#undef COND
1220+
}
1221+
1222+
static void vlv_check_no_gt_access(struct drm_i915_private *dev_priv)
1223+
{
1224+
if (!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEERR))
1225+
return;
1226+
1227+
DRM_ERROR("GT register access while GT waking disabled\n");
1228+
I915_WRITE(VLV_GTLC_PW_STATUS, VLV_GTLC_ALLOWWAKEERR);
1229+
}
1230+
1231+
static int vlv_runtime_suspend(struct drm_i915_private *dev_priv)
1232+
{
1233+
u32 mask;
1234+
int err;
1235+
1236+
/*
1237+
* Bspec defines the following GT well on flags as debug only, so
1238+
* don't treat them as hard failures.
1239+
*/
1240+
(void)vlv_wait_for_gt_wells(dev_priv, false);
1241+
1242+
mask = VLV_GTLC_RENDER_CTX_EXISTS | VLV_GTLC_MEDIA_CTX_EXISTS;
1243+
WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask);
1244+
1245+
vlv_check_no_gt_access(dev_priv);
1246+
1247+
err = vlv_force_gfx_clock(dev_priv, true);
1248+
if (err)
1249+
goto err1;
1250+
1251+
err = vlv_allow_gt_wake(dev_priv, false);
1252+
if (err)
1253+
goto err2;
1254+
vlv_save_gunit_s0ix_state(dev_priv);
1255+
1256+
err = vlv_force_gfx_clock(dev_priv, false);
1257+
if (err)
1258+
goto err2;
1259+
1260+
return 0;
1261+
1262+
err2:
1263+
/* For safety always re-enable waking and disable gfx clock forcing */
1264+
vlv_allow_gt_wake(dev_priv, true);
1265+
err1:
1266+
vlv_force_gfx_clock(dev_priv, false);
1267+
1268+
return err;
1269+
}
1270+
1271+
static int vlv_runtime_resume(struct drm_i915_private *dev_priv)
1272+
{
1273+
struct drm_device *dev = dev_priv->dev;
1274+
int err;
1275+
int ret;
1276+
1277+
/*
1278+
* If any of the steps fail just try to continue, that's the best we
1279+
* can do at this point. Return the first error code (which will also
1280+
* leave RPM permanently disabled).
1281+
*/
1282+
ret = vlv_force_gfx_clock(dev_priv, true);
1283+
1284+
vlv_restore_gunit_s0ix_state(dev_priv);
1285+
1286+
err = vlv_allow_gt_wake(dev_priv, true);
1287+
if (!ret)
1288+
ret = err;
1289+
1290+
err = vlv_force_gfx_clock(dev_priv, false);
1291+
if (!ret)
1292+
ret = err;
1293+
1294+
vlv_check_no_gt_access(dev_priv);
1295+
1296+
intel_init_clock_gating(dev);
1297+
i915_gem_restore_fences(dev);
1298+
1299+
return ret;
1300+
}
1301+
9791302
static int intel_runtime_suspend(struct device *device)
9801303
{
9811304
struct pci_dev *pdev = to_pci_dev(device);
@@ -1003,6 +1326,8 @@ static int intel_runtime_suspend(struct device *device)
10031326
ret = 0;
10041327
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
10051328
ret = hsw_runtime_suspend(dev_priv);
1329+
} else if (IS_VALLEYVIEW(dev)) {
1330+
ret = vlv_runtime_suspend(dev_priv);
10061331
} else {
10071332
ret = -ENODEV;
10081333
WARN_ON(1);
@@ -1051,6 +1376,8 @@ static int intel_runtime_resume(struct device *device)
10511376
ret = snb_runtime_resume(dev_priv);
10521377
} else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
10531378
ret = hsw_runtime_resume(dev_priv);
1379+
} else if (IS_VALLEYVIEW(dev)) {
1380+
ret = vlv_runtime_resume(dev_priv);
10541381
} else {
10551382
WARN_ON(1);
10561383
ret = -ENODEV;

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