8000 Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/… · bsd-unix/linux@612807f · GitHub
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torvaldstorvalds
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Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull perf fixes from Ingo Molnar: "Various fixes: - 32-bit callgraph bug fix - suboptimal event group scheduling bug fix - event constraint fixes for Broadwell/Skylake - RAPL module name collision fix" * 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/core: Fix pmu::filter_match for SW-led groups x86/perf/intel/rapl: Fix module name collision with powercap intel-rapl perf/x86: Fix 32-bit perf user callgraph collection perf/x86/intel: Update event constraints when HT is off
2 parents 977dcf0 + 2c81a64 commit 612807f

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4 files changed

+59
-8
lines changed

4 files changed

+59
-8
lines changed

‎arch/x86/events/core.c

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2319,7 +2319,7 @@ void
23192319
perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs)
23202320
{
23212321
struct stack_frame frame;
2322-
const void __user *fp;
2322+
const unsigned long __user *fp;
23232323

23242324
if (perf_guest_cbs && perf_guest_cbs->is_in_guest()) {
23252325
/* TODO: We don't support guest os callchain now */
@@ -2332,7 +2332,7 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs
23322332
if (regs->flags & (X86_VM_MASK | PERF_EFLAGS_VM))
23332333
return;
23342334

2335-
fp = (void __user *)regs->bp;
2335+
fp = (unsigned long __user *)regs->bp;
23362336

23372337
perf_callchain_store(entry, regs->ip);
23382338

@@ -2345,16 +2345,17 @@ perf_callchain_user(struct perf_callchain_entry_ctx *entry, struct pt_regs *regs
23452345
pagefault_disable();
23462346
while (entry->nr < entry->max_stack) {
23472347
unsigned long bytes;
2348+
23482349
frame.next_frame = NULL;
23492350
frame.return_address = 0;
23502351

2351-
if (!access_ok(VERIFY_READ, fp, 16))
2352+
if (!access_ok(VERIFY_READ, fp, sizeof(*fp) * 2))
23522353
break;
23532354

2354-
bytes = __copy_from_user_nmi(&frame.next_frame, fp, 8);
2355+
bytes = __copy_from_user_nmi(&frame.next_frame, fp, sizeof(*fp));
23552356
if (bytes != 0)
23562357
break;
2357-
bytes = __copy_from_user_nmi(&frame.return_address, fp+8, 8);
2358+
bytes = __copy_from_user_nmi(&frame.return_address, fp + 1, sizeof(*fp));
23582359
if (bytes != 0)
23592360
break;
23602361

‎arch/x86/events/intel/Makefile

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
11
obj-$(CONFIG_CPU_SUP_INTEL) += core.o bts.o cqm.o
22
obj-$(CONFIG_CPU_SUP_INTEL) += ds.o knc.o
33
obj-$(CONFIG_CPU_SUP_INTEL) += lbr.o p4.o p6.o pt.o
4-
obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL) += intel-rapl.o
5-
intel-rapl-objs := rapl.o
4+
obj-$(CONFIG_PERF_EVENTS_INTEL_RAPL) += intel-rapl-perf.o
5+
intel-rapl-perf-objs := rapl.o
66
obj-$(CONFIG_PERF_EVENTS_INTEL_UNCORE) += intel-uncore.o
77
intel-uncore-objs := uncore.o uncore_nhmex.o uncore_snb.o uncore_snbep.o
88
obj-$(CONFIG_PERF_EVENTS_INTEL_CSTATE) += intel-cstate.o

‎arch/x86/events/intel/core.c

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,10 @@ static struct event_constraint intel_snb_event_constraints[] __read_mostly =
115115
INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf), /* CYCLE_ACTIVITY.CYCLES_NO_DISPATCH */
116116
INTEL_UEVENT_CONSTRAINT(0x02a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_PENDING */
117117

118+
/*
119+
* When HT is off these events can only run on the bottom 4 counters
120+
* When HT is on, they are impacted by the HT bug and require EXCL access
121+
*/
118122
INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
119123
INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
120124
INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
@@ -139,6 +143,10 @@ static struct event_constraint intel_ivb_event_constraints[] __read_mostly =
139143
INTEL_UEVENT_CONSTRAINT(0x0ca3, 0x4), /* CYCLE_ACTIVITY.STALLS_L1D_PENDING */
140144
INTEL_UEVENT_CONSTRAINT(0x01c0, 0x2), /* INST_RETIRED.PREC_DIST */
141145

146+
/*
147+
* When HT is off these events can only run on the bottom 4 counters
148+
* When HT is on, they are impacted by the HT bug and require EXCL access
149+
*/
142150
INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
143151
INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
144152
INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
@@ -182,6 +190,16 @@ struct event_constraint intel_skl_event_constraints[] = {
182190
FIXED_EVENT_CONSTRAINT(0x003c, 1), /* CPU_CLK_UNHALTED.CORE */
183191
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
184192
INTEL_UEVENT_CONSTRAINT(0x1c0, 0x2), /* INST_RETIRED.PREC_DIST */
193+
194+
/*
195+
* when HT is off, these can only run on the bottom 4 counters
196+
*/
197+
INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
198+
INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
199+
INTEL_EVENT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_L3_HIT_RETIRED.* */
200+
INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
201+
INTEL_EVENT_CONSTRAINT(0xc6, 0xf), /* FRONTEND_RETIRED.* */
202+
185203
EVENT_CONSTRAINT_END
186204
};
187205

@@ -250,6 +268,10 @@ static struct event_constraint intel_hsw_event_constraints[] = {
250268
/* CYCLE_ACTIVITY.CYCLES_NO_EXECUTE */
251269
INTEL_UEVENT_CONSTRAINT(0x04a3, 0xf),
252270

271+
/*
272+
* When HT is off these events can only run on the bottom 4 counters
273+
* When HT is on, they are impacted by the HT bug and require EXCL access
274+
*/
253275
INTEL_EXCLEVT_CONSTRAINT(0xd0, 0xf), /* MEM_UOPS_RETIRED.* */
254276
INTEL_EXCLEVT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_UOPS_RETIRED.* */
255277
INTEL_EXCLEVT_CONSTRAINT(0xd2, 0xf), /* MEM_LOAD_UOPS_LLC_HIT_RETIRED.* */
@@ -264,6 +286,13 @@ struct event_constraint intel_bdw_event_constraints[] = {
264286
FIXED_EVENT_CONSTRAINT(0x0300, 2), /* CPU_CLK_UNHALTED.REF */
265287
INTEL_UEVENT_CONSTRAINT(0x148, 0x4), /* L1D_PEND_MISS.PENDING */
266288
INTEL_UBIT_EVENT_CONSTRAINT(0x8a3, 0x4), /* CYCLE_ACTIVITY.CYCLES_L1D_MISS */
289+
/*
290+
* when HT is off, these can only run on the bottom 4 counters
291+
*/
292+
INTEL_EVENT_CONSTRAINT(0xd0, 0xf), /* MEM_INST_RETIRED.* */
293+
INTEL_EVENT_CONSTRAINT(0xd1, 0xf), /* MEM_LOAD_RETIRED.* */
294+
INTEL_EVENT_CONSTRAINT(0xd2, 0xf), 1E0A /* MEM_LOAD_L3_HIT_RETIRED.* */
295+
INTEL_EVENT_CONSTRAINT(0xcd, 0xf), /* MEM_TRANS_RETIRED.* */
267296
EVENT_CONSTRAINT_END
268297
};
269298

‎kernel/events/core.c

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1678,12 +1678,33 @@ static bool is_orphaned_event(struct perf_event *event)
16781678
return event->state == PERF_EVENT_STATE_DEAD;
16791679
}
16801680

1681-
static inline int pmu_filter_match(struct perf_event *event)
1681+
static inline int __pmu_filter_match(struct perf_event *event)
16821682
{
16831683
struct pmu *pmu = event->pmu;
16841684
return pmu->filter_match ? pmu->filter_match(event) : 1;
16851685
}
16861686

1687+
/*
1688+
* Check whether we should attempt to schedule an event group based on
1689+
* PMU-specific filtering. An event group can consist of HW and SW events,
1690+
* potentially with a SW leader, so we must check all the filters, to
1691+
* determine whether a group is schedulable:
1692+
*/
1693+
static inline int pmu_filter_match(struct perf_event *event)
1694+
{
1695+
struct perf_event *child;
1696+
1697+
if (!__pmu_filter_match(event))
1698+
return 0;
1699+
1700+
list_for_each_entry(child, &event->sibling_list, group_entry) {
1701+
if (!__pmu_filter_match(child))
1702+
return 0;
1703+
}
1704+
1705+
return 1;
1706+
}
1707+
16871708
static inline int
16881709
event_filter_match(struct perf_event *event)
16891710
{

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