8000 arm64: Enable workaround for Cavium erratum 27456 on thunderx-81xx · bsd-unix/linux@47c459b · GitHub
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Ganapatrao Kulkarniwildea01
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arm64: Enable workaround for Cavium erratum 27456 on thunderx-81xx
Cavium erratum 27456 commit 104a0c0 ("arm64: Add workaround for Cavium erratum 27456") is applicable for thunderx-81xx pass1.0 SoC as well. Adding code to enable to 81xx. Signed-off-by: Ganapatrao Kulkarni <gkulkarni@cavium.com> Reviewed-by: Andrew Pinski <apinski@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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arch/arm64/include/asm/cputype.h

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@@ -80,12 +80,14 @@
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#define APM_CPU_PART_POTENZA 0x000
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#define CAVIUM_CPU_PART_THUNDERX 0x0A1
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#define CAVIUM_CPU_PART_THUNDERX_81XX 0x0A2
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#define BRCM_CPU_PART_VULCAN 0x516
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#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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#ifndef __ASSEMBLY__
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arch/arm64/kernel/cpu_errata.c

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@@ -98,6 +98,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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MIDR_RANGE(MIDR_THUNDERX, 0x00,
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(1 << MIDR_VARIANT_SHIFT) | 1),
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},
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{
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/* Cavium ThunderX, T81 pass 1.0 */
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.desc = "Cavium erratum 27456",
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.capability = ARM64_WORKAROUND_CAVIUM_27456,
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MIDR_RANGE(MIDR_THUNDERX_81XX, 0x00, 0x00),
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},
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#endif
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{
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}

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