8000 stm32h7_m4: fix clock configuration for Giga · arduino/ArduinoCore-mbed@d6a2326 · GitHub
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stm32h7_m4: fix clock configuration for Giga
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2 files changed

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‎mbed-os-to-arduino

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@@ -219,6 +219,9 @@ generate_flags () {
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sed -i 's/LENGTH = 0x200000/LENGTH = CM4_BINARY_END - CM4_BINARY_START/g' "$ARDUINOVARIANT"/linker_script.ld
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sed -i 's/LENGTH = 0x1c0000/LENGTH = CM4_BINARY_START - 0x8040000/g' "$ARDUINOVARIANT"/linker_script.ld
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fi
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if [[ $ARDUINOVARIANT == *PORTENTA_H7_M4* ]]; then
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arm-none-eabi-objcopy -W HAL_RCC_GetSysClockFreq "$ARDUINOVARIANT"/libs/libmbed.a "$ARDUINOVARIANT"/libs/libmbed.a
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fi
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if [[ $ARDUINOVARIANT == *NANO_RP2040* ]]; then
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set +e
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HAS_2NDSTAGE_SECTION=`grep second_stage_ota "$ARDUINOVARIANT"/linker_script.ld`

‎variants/PORTENTA_H7_M4/clock_override.cpp

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#include "Arduino.h"
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#if defined(GIGA_PINS)
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#undef HSE_VALUE
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#define HSE_VALUE 16000000
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#endif
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extern "C" uint32_t HAL_RCC_GetSysClockFreq(void)
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{
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uint32_t pllp, pllsource, pllm, pllfracen, hsivalue;
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float_t fracn1, pllvco;
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uint32_t sysclockfreq;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
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if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
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{
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sysclockfreq = (uint32_t) (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
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}
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else
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{
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sysclockfreq = (uint32_t) HSI_VALUE;
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}
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break;
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case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
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sysclockfreq = CSI_VALUE;
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break;
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case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
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sysclockfreq = HSE_VALUE;
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break;
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case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
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pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
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pllfracen = ((RCC-> PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
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fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
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if (pllm != 0U)
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{
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switch (pllsource)
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{
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case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
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if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIDIV) != 0U)
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{
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hsivalue= (HSI_VALUE >> (__HAL_RCC_GET_HSI_DIVIDER()>> 3));
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pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
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}
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else
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{
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pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
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}
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break;
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case RCC_PLLSOURCE_CSI: /* CSI used as PLL clock source */
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pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
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break;
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case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
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pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
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break;
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default:
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pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
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break;
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}
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pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
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sysclockfreq = (uint32_t)(float_t)(pllvco/(float_t)pllp);
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}
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else
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{
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sysclockfreq = 0U;
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}
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break;
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default:
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sysclockfreq = CSI_VALUE;
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break;
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}
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return sysclockfreq;
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}

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