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| 1 | +// This file is part of the CircuitPython project: https://circuitpython.org |
| 2 | +// |
| 3 | +// SPDX-FileCopyrightText: Copyright (c) 2021 Scott Shawcroft for Adafruit Industries |
| 4 | +// |
| 5 | +// SPDX-License-Identifier: MIT |
| 6 | + |
| 7 | +#include "supervisor/board.h" |
| 8 | +#include "mpconfigboard.h" |
| 9 | +#include "shared-bindings/busio/SPI.h" |
| 10 | +#include "shared-bindings/fourwire/FourWire.h" |
| 11 | +#include "shared-module/displayio/__init__.h" |
| 12 | +#include "shared-module/displayio/mipi_constants.h" |
| 13 | +#include "supervisor/shared/board.h" |
| 14 | + |
| 15 | +// Use the MP_WEAK supervisor/shared/board.c versions of routines not defined here. |
| 16 | +#define DELAY 0x80 |
| 17 | + |
| 18 | +uint8_t display_init_sequence[] = { |
| 19 | + 0x01, 0 | DELAY, 120, // SWRESET |
| 20 | + 0x11, 0 | DELAY, 120, // SWRESET |
| 21 | + |
| 22 | + 0x36, 1, 0x70, // MADCTL |
| 23 | + 0x3A, 1, 0x55, // COLMOD |
| 24 | + 0xB2, 5, 0x0C, 0x0C, 0x00, 0x33, 0x33, // FRMCTR2 |
| 25 | + 0xB7, 1, 0x75, // GCTRL |
| 26 | + 0xBB, 1, 0x2B, // VCOMS |
| 27 | + 0xC0, 1, 0x2C, // LCMCTRL |
| 28 | + 0xC2, 1, 0x01, // VDVVRHEN |
| 29 | + 0xC3, 1, 0x0B, // VRHS |
| 30 | + 0xC4, 1, 0x20, // VDVS |
| 31 | + 0xC6, 1, 0x0F, // FRCTRL2 |
| 32 | + 0xD0, 2, 0xA4, 0xA1, // PWRCTRL1 |
| 33 | + |
| 34 | + 0xE0, 14, 0xD0, 0x01, 0x04, 0x09, 0x0B, 0x07, 0x2E, 0x44, 0x43, 0x0B, 0x16, 0x15, 0x17, 0x1D, // GMCTRP1 |
| 35 | + 0xE1, 14, 0xD0, 0x01, 0x05, 0x0A, 0x0B, 0x08, 0x2F, 0x44, 0x41, 0x0A, 0x15, 0x14, 0x19, 0x1D, // GMCTRN1 |
| 36 | + 0x29, 0 | DELAY, 120, // DISPON |
| 37 | + |
| 38 | + // 0x2A, 4, 0x00, 0, 0x01, 0x3F, // CASET |
| 39 | + // 0x2B, 4, 0x00, 0, 0x00, 0xEF, // RASET |
| 40 | + // 0x2C, 0, // RAMWR |
| 41 | +}; |
| 42 | + |
| 43 | +static void display_init(void) { |
| 44 | + fourwire_fourwire_obj_t *bus = &allocate_display_bus()->fourwire_bus; |
| 45 | + busio_spi_obj_t *spi = &bus->inline_bus; |
| 46 | + |
| 47 | + common_hal_busio_spi_construct( |
| 48 | + spi, |
| 49 | + &pin_GPIO2, // CLK |
| 50 | + &pin_GPIO3, // MOSI |
| 51 | + &pin_GPIO0, // MISO |
| 52 | + false); // Not half-duplex |
| 53 | + |
| 54 | + common_hal_busio_spi_never_reset(spi); |
| 55 | + |
| 56 | + bus->base.type = &fourwire_fourwire_type; |
| 57 | + |
| 58 | + common_hal_fourwire_fourwire_construct( |
| 59 | + bus, |
| 60 | + spi, |
| 61 | + &pin_GPIO0, // DC |
| 62 | + &pin_GPIO1, // CS |
| 63 | + &pin_GPIO4, // RST |
| 64 | + 62.5 * 1000 * 1000, // baudrate |
| 65 | + 0, // polarity |
| 66 | + 0 // phase |
| 67 | + ); |
| 68 | + |
| 69 | + busdisplay_busdisplay_obj_t *display = &allocate_display()->display; |
| 70 | + display->base.type = &busdisplay_busdisplay_type; |
| 71 | + |
| 72 | + common_hal_busdisplay_busdisplay_construct( |
| 73 | + display, |
| 74 | + bus, |
| 75 | + 320, // width (after rotation) |
| 76 | + 240, // height (after rotation) |
| 77 | + 0, // column start |
| 78 | + 0, // row start |
| 79 | + 0, // rotation |
| 80 | + 16, // color depth |
| 81 | + false, // grayscale |
| 82 | + false, // pixels in a byte share a row. Only valid for depths < 8 |
| 83 | + 1, // bytes per cell. Only valid for depths < 8 |
| 84 | + false, // reverse_pixels_in_byte. Only valid for depths < 8 |
| 85 | + true, // reverse_pixels_in_word |
| 86 | + MIPI_COMMAND_SET_COLUMN_ADDRESS, // set column command |
| 87 | + MIPI_COMMAND_SET_PAGE_ADDRESS, // set row command |
| 88 | + MIPI_COMMAND_WRITE_MEMORY_START, // write memory command |
| 89 | + display_init_sequence, |
| 90 | + sizeof(display_init_sequence), |
| 91 | + NULL, // backlight pin |
| 92 | + NO_BRIGHTNESS_COMMAND, |
| 93 | + 1.0f, // brightness |
| 94 | + false, // single_byte_bounds |
| 95 | + false, // data_as_commands |
| 96 | + true, // auto_refresh |
| 97 | + 60, // native_frames_per_second |
| 98 | + true, // backlight_on_high |
| 99 | + false, // SH1107_addressing |
| 100 | + 50000 // backlight pwm frequency |
| 101 | + ); |
| 102 | + |
| 103 | +} |
| 104 | + |
| 105 | +void board_init(void) { |
| 106 | + display_init(); |
| 107 | +} |
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