8000 Schematic Viewer fails (GHDL + Yosys, Windows) · Issue #717 · TerosTechnology/vscode-terosHDL · GitHub
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Schematic Viewer fails (GHDL + Yosys, Windows) #717

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gfcwfzkm opened this issue Jan 20, 2025 · 3 comments
Open

Schematic Viewer fails (GHDL + Yosys, Windows) #717

gfcwfzkm opened this issue Jan 20, 2025 · 3 comments
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bug Something isn't working

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@gfcwfzkm
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Describe the bug
The schematic viewer fails on windows for VHDL (GHDL + YOSYS):

2025-01-20 11:17:17.731 [info] Executing: C:\Windows\system32\cmd.exe  C:\Windows\system32\cmd.exe /d /s /c " C:\msys64\ucrt64\bin\yosys.exe -m ghdl -p "ghdl --std=08 -fsynopsys  --work=work "c:\Users\WDAGUtilityAccount\.vscode\extensions\teros-technology.teroshdl-6.0.14\resources\project_manager\examples\ghdl\half_adder.vhd"  --work=work -e half_adder; hierarchy -top half_adder; proc; write_json C:\Users\WDAGUtilityAccount\.teroshdl_8RZk0; stat""
2025-01-20 11:17:17.963 [info] ERROR: Can't load module `./ghdl': "C:\msys64\ucrt64\bin\..\share\yosys\plugins\ghdl.so": The specified module could not be found.
2025-01-20 11:17:17.971 [error] Yosys failed.

The bug report also applies when trying to execute the schematic viewer from the hierarchy.

To Reproduce
GHDL and Yosys (as well as GNU Make and GTKWave) were installed using MSYS2 UCRT64 with the following command:

pacman -S make mingw-w64-ucrt-x86_64-make mingw-w64-ucrt-x86_64-ghdl-llvm mingw-w64-ucrt-x86_64-gtkwave mingw-w64-ucrt-x86_64-yosys

The binary paths to Yosys and GHDL are both set to C:\msys64\ucrt64\bin and performing the "Verify Setup" task successfully detects them.

Is this a good way to install GHDL + Yosys on Windows? If not, what would be better? I'm using MSYS2 to benefit from an simple update system via pacman but if there is a more reliable way to use GHDL+Yosys with TerosHDL, I'm open for it.

Code
The error can be reproduced with the GHDL example included by TerosHDL.

Please complete the following information:

  • OS: Windows 11 Enterprise and Windows 11 Pro
  • VSCode version: 1.96.4
  • TerosHDL version: 6.0.14

Additional context
If I perform the command in CMD manually, but remove -m ghdl from the command, it seems that everything performs as expected and a JSON file is written.

C:\Windows\system32\cmd.exe /d /s /c " C:\msys64\ucrt64\bin\yosys.exe -p "ghdl --std=08 -fsynopsys  --work=work "c:\Users\WDAGUtilityAccount\.vscode\extensions\teros-technology.teroshdl-6.0.14\resources\project_manager\examples\ghdl\half_adder.vhd"  --work=work -e half_adder; hierarchy -top half_adder; proc; write_json C:\Users\WDAGUtilityAccount\.teroshdl_8RZk0; stat""

It seems that the MSYS2 versions of Yosys and GHDL don't ship GHDL as shared library (there is no \share\yosys folder either), yet executing ghdl within Yosys performs just fine.
@gfcwfzkm gfcwfzkm added the bug Something isn't working label Jan 20, 2025
@JakubFranek
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Hello

I have the same issue.

I think the problem is a bug in TerosHDL. The MSYS2 version of yosys, (package mingw-w64-yosys to be exact), already contains ghdl-yosys-plugin built into yosys (see this file for proof).

Therefore installing yosys this way does not create any plugins/ghdl.so file. The ghdl integration is now baked into yosys and creating the schematic diagram should be invoked somehow differently by the TerosHDL extension. I do not know how, but as of now the schematic viewer on Windows is not usable.

I will be happy to learn any workaround. Thank you!

Jakub

@qarlosalberto
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Could you share an example?

@JakubFranek
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Hello @qarlosalberto, what kind of example do you have in mind?

I installed ghdl and yosys (with a built-in ghdl-yosys-plugin) via MSYS2 from the mingw-w64-x86_64-eda package group. This installation creates working yosys and ghdl, but it does not create any ghdl.so file, which TerosHDL expects. This creates the following error when attempting to view a schematic diagram of a VHDL code within TersosHDL:

2025-02-16 21:06:06.483 [info] Executing: C:\WINDOWS\system32\cmd.exe C:\WINDOWS\system32\cmd.exe /d /s /c " D:\Programy\MSYS2\mingw64\bin\yosys.exe -m ghdl -p "ghdl --std=08 -fsynopsys --work=work "d:\Electronics\FPGA\nexys-a7-lab\source\common\clock_enable_generator.vhd" --work=work -e clock_enable_generator; hierarchy -top clock_enable_generator; proc; write_json C:\Users\jfran.teroshdl_wfim2; stat""
2025-02-16 21:06:06.548 [info] ERROR: Can't load module `./ghdl': "D:\Programy\MSYS2\mingw64\bin..\share\yosys\plugins\ghdl.so": Uveden� modul nebyl nalezen.

2025-02-16 21:06:06.550 [info]
/----------------------------------------------------------------------------
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf claire@yosyshq.com |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
----------------------------------------------------------------------------/

Yosys 0.38 (git sha1 543faed9c8c, x86_64-w64-mingw32-g++ 13.2.0 -march=nocona -msahf -mtune=generic -O2 -fstack-protector-strong -Os)

2025-02-16 21:06:06.555 [error] Yosys failed.

The original poster of this issues says that removing -m ghdl from the command fixed the issue for him, so I tried it.

I had to clean up the command a little bit into this form first:
D:/Programy/MSYS2/mingw64/bin/yosys.exe -p "ghdl --std=08 -fsynopsys --work=work d:/Electronics/FPGA/nexys-a7-lab/source/common/clock_enable_generator.vhd --work=work -e clock_enable_generator; hierarchy -top clock_enable_generator; proc; write_json C:/Users/jfran/.teroshdl_gyYxC; stat"

When I ran it, I got this:

jfran@Lenovo-Y530 MINGW64 /d/Electronics/FPGA/nexys-a7-lab (master)
$ D:/Programy/MSYS2/mingw64/bin/yosys.exe -p "ghdl --std=08 -fsynopsys --work=work d:/Electronics/FPGA/nexys-a7-lab/source/common/clock_enable_generator.vhd --work=work -e clock_enable_generator; hierarchy -top clock_enable_generator; proc; write_json C:/Users/jfran/.teroshdl_gyYxC; stat"

/----------------------------------------------------------------------------
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2020 Claire Xenia Wolf claire@yosyshq.com |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
----------------------------------------------------------------------------/

Yosys 0.38 (git sha1 543faed9c8c, x86_64-w64-mingw32-g++ 13.2.0 -march=nocona -msahf -mtune=generic -O2 -fstack-protector-strong -Os)

-- Running command `ghdl --std=08 -fsynopsys --work=work d:/Electronics/FPGA/nexys-a7-lab/source/common/clock_enable_generator.vhd --work=work -e clock_enable_generator; hierarchy -top
clock_enable_generator; proc; write_json C:/Users/jfran/.teroshdl_gyYxC; stat' --

  1. Executing GHDL.
    Importing module clock_enable_generator.

  2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module: \clock_enable_generator

2.2. Analyzing design hierarchy..
Top module: \clock_enable_generator
Removed 0 unused modules.

  1. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module clock_enable_generator.

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module clock_enable_generator.

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module clock_enable_generator.
3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module clock_enable_generator.

  1. Executing JSON backend.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module clock_enable_generator.

  1. Executing JSON backend.

  2. Printing statistics.

  3. Executing JSON backend.

  4. Printing statistics.

  5. Printing statistics.

  6. Printing statistics.

=== clock_enable_generator ===

=== clock_enable_generator ===

Number of wires: 9
Number of wire bits: 113
=== clock_enable_generator ===

Number of wires: 9
Number of wire bits: 113

Number of wires: 9
Number of wire bits: 113
Number of wires: 9
Number of wire bits: 113
Number of public wires: 3
Number of public wires: 3
Number of public wire bits: 29
Number of memories: 0
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 6
$add 1
Number of processes: 0
Number of cells: 6
$add 1
$dff 2
$eq 1
$mux 2
Number of cells: 6
$add 1
$dff 2
$eq 1
$mux 2
$dff 2
$eq 1
$mux 2

End of script. Logfile hash: 673d44aea0
$eq 1
$mux 2

End of script. Logfile hash: 673d44aea0

End of script. Logfile hash: 673d44aea0
Yosys 0.38 (git sha1 543faed9c8c, x86_64-w64-mingw32-g++ 13.2.0 -march=nocona -msahf -mtune=generic -O2 -fstack-protector-strong -Os)
End of script. Logfile hash: 673d44aea0
Yosys 0.38 (git sha1 543faed9c8c, x86_64-w64-mingw32-g++ 13.2.0 -march=nocona -msahf -mtune=generic -O2 -fstack-protector-strong -Os)
Yosys 0.38 (git sha1 543faed9c8c, x86_64-w64-mingw32-g++ 13.2.0 -march=nocona -msahf -mtune=generic -O2 -fstack-protector-strong -Os)
Time spent: 6% 2x write_json (0 sec), 6% 2x proc_clean (0 sec), ...

It seems that the operation was successful. Therefore I would propose to create another GHDL+Yosys option in the TerosHDL Global Settings/Schematic viewer/Backend, which would send nearly the same command as it does now, but without the -m ghdl.

Hope it makes sense and hope it works for others as well. Please let me know if you need any further information.

Kind regards
Jakub

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@gfcwfzkm @qarlosalberto @JakubFranek
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