OSVVM is a verification framework, VHDL utility library, VHDL Verification component library, and a scripting flow that provides the same capabilities that verification languages such as SystemVerilog + UVM support.
OSVVM is developed by the same VHDL experts who have helped develop VHDL standards. We have used our expert VHDL skills to create advanced verification capabilities that are easy to use.
You can find an overview of OSVVM at osvvm.github.io. Alternately you can find our pdf documentation at OSVVM Documentation Repository.
You can also learn OSVVM by taking the class, Advanced VHDL Verification and Testbenches - OSVVM™ BootCamp
OSVVM is available as either a git repository OsvvmLibraries or zip file from osvvm.org Downloads Page.
On GitHub, all OSVVM libraries are a submodule of the repository OsvvmLibraries. Download all OSVVM libraries using git clone with the “–recursive” flag:
$ git clone --recursive https://github.com/osvvm/OsvvmLibraries
A great way to get oriented with OSVVM is to run the demos. For directions on running the demos, see OSVVM Scripts.
The OSVVM Utility library implements verification capabilities such as:
- Transaction-Level Modeling (TbUtilPkg, ResolutionPkg)
- Constrained Random test generation (RandomPkg)
- Functional Coverage with hooks for UCIS coverage database integration (CoveragePkg)
- Intelligent Coverage Random test generation (CoveragePkg)
- Utilities for testbench process synchronization generation (TbUtilPkg)
- Utilities for clock and reset generation (TbUtilPkg)
- Transcript files (TranscriptPkg)
- Error logging and reporting - Alerts and Affirmations (AlertLogPkg)
- Message filtering - Logs (AlertLogPkg)
- Scoreboards and FIFOs (data structures for verification) (ScoreboardGenericPkg)
- Memory models (MemoryPkg)
For details see the OSVVM Utility Library README.
- OSVVM's simulator independent scripting approach.
- Supports Aldec's Riviera-PRO/Active-HDL, Siemen's QuestaSim/ModelSim, GHDL, Synopsys' VCS, and Cadence's Xcelium
OSVVM Verification components are all independent git repositories.
- Defines OSVVMs Model Independent Transactions (Address Bus and Stream)
- Required for all OSVVM Verification Components
- Axi4 Full Manager, Memory, Subordinate Verification Components
- Axi4 Lite Manager and Subordinate Verification Components
- AxiStream Transmitter and Receiver Verification Components
- UART Transmitter and Receiver
- DpRam behavioral model
- DpRam Manager VC to read and write to the DpRam interface