A place to keep my synthesizable verilog examples.
Table of Contents
- OVERVIEW
- BASIC CODE
- COMBINATIONAL LOGIC
- SEQUENTIAL LOGIC
- COMBINATIONAL LOGIC
- ALUs
- DATA OPERATORS
- DECODERS & ENCODERS
- MULTIPLEXERS & DEMULTIPLEXERS
- FPGA DEVELOPMENT BOARDS
- BUTTONS
- SEQUENTIAL LOGIC
- ARBITERS
- COUNTERS
- FINITE SATE MACHINES
- MEMORY
- REGISTERS
- SHIFTERS
- SYSTEMS
- MICROPROCESSORS
- PIPELINES
Documentation and Reference
- verilog cheat sheet
- iverilog is a free tool for simulation and synthesis
- GTKWave is a free HDL waveform viewer
- xilinx vivado is a complete IDE for synthesis and analysis of HDL designs
- digilent ARTY-S7 is a FPGA development board
- My Master's Thesis has an explanation of HDLs and how they fit into frameworks
- My Master's Thesis also has my design of a programable_8_bit_microprocessor
- This repos github webpage built with concourse
Each example uses iverilog to simulate and GTKWave to view the waveform. I also used Xilinx Vivado to synthesize and program these verilog examples on a Digilent ARTY-S7 FPGA development board.
I declare my ports as follows because that's what the synthesis tools want. Who am I to argue.
module NAME (
input a, // Input A
input [7:0] b, // Input B
output reg [3:0] y); // Output YAlso, I would stay away from asynchronous design. It can have problems when you synthesize to an FPGA.
// DO THIS
always @(posedge clk) begin
if (~reset) begin
...
// NOT THIS
always @(posedge clk or negedge reset) begin
Each example has the following 4 files,
*.v- The verilog code files(s)*.vh- A header file listing the included verilog files*_tb.v- The verilog testbench code*_tb.tv- Test vectors used with the testbench
The artifacts created are,
*_tb.vvp- The verilog compiled code to be used by the simulator*_tb.vcd- The dump of the waveform data*_tb.gtkw- The GTKWave saved waveform
Where the testbench structure is,
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COMBINATIONAL LOGIC
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2-input AND gate used in my programable_8_bit_microprocessor.
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4-input NAND gate used in my programable_8_bit_microprocessor.
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2-input NOR gate used in my programable_8_bit_microprocessor.
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NOT gate used in my programable_8_bit_microprocessor.
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2-input OR gate used in my programable_8_bit_microprocessor.
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2-input XOR gate used in my programable_8_bit_microprocessor.
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SEQUENTIAL LOGIC
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A sr (set ready) latch which is level-triggered that can be set and reset. The latch forms the basic building block of other types of latches and flip-flops.
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A sr (set ready) flip-flop which is pulse-triggered can be set and reset.
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A jk flip-flop which is pulse-triggered can be set, reset and toggled. This has a race condition when clock is high.
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A pulse-triggered jk flip-flop (cascading) can be set, reset and toggled.
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jk_flip_flop_pos_edge_sync_clear
A posedge-triggered jk flip-flop with synchronous clear used in my jeff_74x161.
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A t flip-flop which is pulse-triggered can be toggled. This has a race condition when clock is high.
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A d flip-flop which is pulse-triggered can save input data on output.
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A pulse-triggered d flip-flop (cascading) can save input data on output.
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A posedge-triggered d flip-flop with synchronous enable used in my jeff_74x377.
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ALUs
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4-bit alu (arithmetic logic unit) and function generator. Provides 16 binary logic operations and 16 arithmetic operations on two 4-bit words. Based on the 7400-series integrated circuits used in my programable_8_bit_microprocessor.
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DATA OPERATORS
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A 2-bit full-adder.
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A 2-bit half-adder.
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DECODERS & ENCODERS
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Encoder - Eights inputs (1 hot) encodes to output.
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Decoder - Three inputs decodes to 1 of 8 outputs (hot).
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Combining the encoder_8_3 to the decoder_3_8 to prove the input will equal the output.
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MULTIPLEXERS & DEMULTIPLEXERS
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Demultiplexer - One input, four outputs.
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8-line to 1-line data selector/multiplexer. Based on the 7400-series integrated circuits used in my programable_8_bit_microprocessor.
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Quad 2-line to 1-line data selector/multiplexer, non-inverting outputs. Based on the 7400-series integrated circuits used in my programable_8_bit_microprocessor.
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Multiplexer - Four inputs, one output.
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Combining the mux_4x1 to the demux_1x4 to prove the input will equal the output (for the selected output).
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BUTTONS
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A few different ways to use buttons on a FPGA development board.
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ARBITERS
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A three level priority arbiter with asynchronous reset.
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COUNTERS
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Synchronous presettable 4-bit binary counter, asynchronous clear. Based on the 7400-series integrated circuits used in my programable_8_bit_microprocessor.
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FINITE STATE MACHINES
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Recognize the pattern 00110 in a serial stream. Output depends on current state and current inputs.
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Recognize the pattern 00110 in a serial stream. Output depends on current state only.
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MEMORY
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Single-port synchronous RAM.
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Dual-port synchronous RAM.
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Dual-port asynchronous RAM using two different clocks.
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A synchronous fifo using dual-port synchronous RAM.
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An asynchronous fifo using dual-port asynchronous RAM.
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A synchronous lifo using dual-port synchronous RAM.
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REGISTERS
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8-bit register, clock enable. Based on the 7400-series integrated circuits used in my programable_8_bit_microprocessor.
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A simple 8-bit register with synchronous load and clear.
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SHIFTERS
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A 4-bit left shift register.
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MICROPROCESSORS
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programable_8_bit_microprocessor
A programable 8-bit microprocessor. Originally designed in VHDL for part of my master's thesis.
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PIPELINES
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A simple pipeline.
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