8000 Converted target code to use CMSIS. · AKrduino/arduino-stm32@7d91e0c · GitHub
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mlumlu
committed
Converted target code to use CMSIS.
Compiles, not tested.
1 parent 341ae1b commit 7d91e0c

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11 files changed

+109
-74
lines changed

11 files changed

+109
-74
lines changed

‎hardware/cores/stm32/HardwareSerial.cpp

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,9 @@
2727
#include "wiring_private.h"
2828

2929
#include "HardwareSerial.h"
30-
#include "stm32f10x_rcc.h"
31-
#include "stm32f10x_usart.h"
32-
#include "stm32f10x_nvic.h"
30+
//#include "stm32f10x_rcc.h"
31+
//#include "stm32f10x_usart.h"
32+
//#include "stm32f10x_nvic.h"
3333
#define USART_Enable 0x2000
3434
#define USART_RXNEIE 0x0020
3535

@@ -104,25 +104,28 @@ void HardwareSerial::begin(long speed)
104104
// Enable perhipherial clock
105105
if (_usart == USART1 )
106106
{
107-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
108-
NVIC->ISER[USART1_IRQChannel/32] = (1<<(USART1_IRQChannel%32));
107+
RCC->APB2ENR = RCC_APB2ENR_USART1EN;
108+
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
109+
NVIC->ISER[USART1_IRQn/32] = (1<<(USART1_IRQn%32));
109110
// Configure peripherial pins, TX - PA9, RX - PA10
110111
GPIOA->CRH = (GPIOA->CRH & 0xFFFFF00F) | 0x000004A0;
111112
}
112113
if (_usart == USART2 )
113114
{
114115
// USART2 runs on APB1 clock which is HCLK/2 = 36 MHz
115-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
116-
NVIC->ISER[USART2_IRQChannel/32] = (1<<(USART2_IRQChannel%32));
116+
RCC->APB1ENR = RCC_APB1ENR_USART2EN;
117+
// RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
118+
NVIC->ISER[USART2_IRQn/32] = (1<<(USART2_IRQn%32));
117119
speed = speed*2;
118120
// Configure peripherial pins, TX - PA2, RX - PA3
119121
GPIOA->CRL = (GPIOA->CRL & 0xFFFF00FF) | 0x00004A00;
120122
}
121123
if (_usart == USART3 )
122124
{
123125
// USART3 runs on APB1 clock which is HCLK/2 = 36 MHz
124-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
125-
NVIC->ISER[USART3_IRQChannel/32] = (1<<(USART3_IRQChannel%32));
126+
RCC->APB1ENR = RCC_APB1ENR_USART3EN;
127+
// RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE);
128+
NVIC->ISER[USART3_IRQn/32] = (1<<(USART3_IRQn%32));
126129
speed = speed*2;
127130
// Configure peripherial pins, TX - PB10, RX - PB11
128131
GPIOB->CRH = (GPIOB->CRH & 0xFFFF00FF) | 0x00004A00;
@@ -133,7 +136,7 @@ void HardwareSerial::begin(long speed)
133136
_usart->CR3 = 0;
134137
_usart->SR = 0;
135138
_usart->BRR = MCK / speed;
136-
_usart->CR1 = USART_Mode_Rx | USART_Mode_Tx | USART_RXNEIE | USART_Enable;
139+
_usart->CR1 = USART_CR1_RE | USART_CR1_TE | USART_RXNEIE | USART_CR1_UE;
137140

138141
}
139142

@@ -170,7 +173,7 @@ void HardwareSerial::flush()
170173

171174
void HardwareSerial::write(< 9E88 span class="pl-c1">uint8_t c)
172175
{
173-
while (!(_usart->SR & USART_FLAG_TXE))
176+
while (!(_usart->SR & USART_SR_TXE))
174177
;
175178

176179
_usart->DR = c;

‎hardware/cores/stm32/HardwareSerial.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@
2323
#include <inttypes.h>
2424

2525
#include "Print.h"
26-
#include "stm32f10x_map.h"
26+
#include "stm32f10x.h"
2727

2828
struct ring_buffer;
2929

‎hardware/cores/stm32/HardwareSpi.cpp

Lines changed: 51 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,22 @@
11
#include <unistd.h>
22
#include "HardwareSpi.h"
3+
#include "wiring_private.h"< F438 /div>
34

5+
/************************************************************************
6+
How do we handle slave select ?
7+
8+
Client code uses digitalWrite(CSpin, 0/1) ?
9+
10+
Client code calls spi->select()/deselect() ?
11+
12+
The select pin is not an attribute of the Spi interface, it is rather the
13+
attibute of a connected Spi slave unit. The SpiSlave class uses a Spi interface
14+
and when the slave calls select then all other slaves using the same Spi interface
15+
must be deselected.
16+
17+
Each Spi slave can also have different mode and bitorder settings.
18+
19+
************************************************************************/
420
uint8_t Spi::txrx(const uint8_t * dataout, uint8_t * datain, int count)
521
{
622
uint8_t recv,send=0xFF;
@@ -27,6 +43,7 @@ uint8_t Spi::tx(uint8_t * dataout,int count)
2743
/*******************************/
2844
/* Hardware SPI implementation */
2945
/*******************************/
46+
#define SPE 0x0040
3047

3148
HardwareSpi::HardwareSpi(SPI_TypeDef * _spi)
3249
{
@@ -39,16 +56,47 @@ HardwareSpi::HardwareSpi(SPI_TypeDef * _spi)
3956

4057
};
4158

42-
void HardwareSpi::begin()
59+
void HardwareSpi::begin(/* khz, master*/)
4360
{
44-
61+
// Enable perhipherial clock
62+
if (spi == SPI1 )
63+
{
64+
RCC->APB2ENR = RCC_APB2ENR_SPI1EN;
65+
// RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE);
66+
// NVIC->ISER[SPI1_IRQChannel/32] = (1<<(SPI1_IRQChannel%32));
67+
// Configure peripherial pins, NSS - PA4, SCK - PA5, MISO - PA6, MOSI PA7
68+
// Master does not use NSS
69+
GPIOA->CRL = (GPIOA->CRL & 0x000FFFFF) | 0xA4A00000;
70+
}
71+
if (spi == SPI2 )
72+
{
73+
// USART2 runs on APB1 clock which is HCLK/2 = 36 MHz
74+
RCC->APB1ENR = RCC_APB1ENR_SPI2EN;
75+
// RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE);
76+
// NVIC->ISER[SPI2_IRQChannel/32] = (1<<(SPI2_IRQChannel%32));
77+
// Configure peripherial pins, NSS - PB12, SCK - PB13, MISO - PB14, MOSI PB15
78+
// Master does not use NSS
79+
GPIOB->CRH = (GPIOB->CRH & 0x000FFFFF) | 0xA4A00000;
80+
}
81+
if (spi == SPI3 )
82+
{
83+
// USART3 runs on APB1 clock which is HCLK/2 = 36 MHz
84+
RCC->APB1ENR = RCC_APB1ENR_SPI3EN;
85+
// RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);
86+
// NVIC->ISER[SPI2_IRQChannel/32] = (1<<(SPI2_IRQChannel%32));
87+
// Configure peripherial pins, NSS - PA15, SCK - PB3, MISO - PB4, MOSI PB5
88+
// Master does not use NSS
89+
GPIOB->CRL = (GPIOB->CRL & 0xFF000FFF) | 0x00A4A000;
90+
}
91+
spi->CR1 = SPI_CR1_SPE | SPI_CR1_SSM | SPI_CR1_MSTR | SPI_BaudRatePrescaler_64; /* LSB | SSM | SSI | ENABLE | MASTER | BAUDRATE | POLARITY | PHASE */
92+
spi->CR2 = 0;
4593
};
4694

4795
uint8_t HardwareSpi::txrx_byte(uint8_t dataout)
4896
{
4997
uint8_t datain;
5098
spi->DR = dataout;
51-
while (spi->SR & 0x1) {};
99+
while (spi->SR & SPI_SR_RXNE) {};
52100
datain = spi->DR;
53101
return datain;
54102
};

‎hardware/cores/stm32/HardwareSpi.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
#include <inttypes.h>
55

66
#include "Spi.h"
7-
#include "stm32f10x_map.h"
7+
#include "stm32f10x.h"
88

99
class HardwareSpi : public Spi
1010
{

‎hardware/cores/stm32/MMC.cpp

Lines changed: 13 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -20,10 +20,10 @@ uint8_t MMC::wait_response(uint8_t response, uint8_t mask)
2020
uint8_t din;
2121
timeout = 500; /* Wait for ready in timeout of 500ms */
2222

23-
din = spi->txrx_byte(0xFF);
23+
din = spi.txrx_byte(0xFF);
2424
while (( (din&mask) != (response&mask) ) && timeout)
2525
{
26-
din = spi->txrx_byte(0xFF);
26+
din = spi.txrx_byte(0xFF);
2727
};
2828
return din;
2929
};
@@ -33,27 +33,27 @@ uint8_t MMC::command_response (const uint8_t *cmd, uint8_t * rspdata, int rsplen
3333
int count, retry=0;
3434
uint8_t rxchar;
3535

36-
spi->select();
36+
spi.select();
3737
if (wait_response(READY_TOKEN, READY_TOKEN) != READY_TOKEN)
3838
{
39-
spi->deselect();
39+
spi.deselect();
4040
return 0xFF;
4141
}
4242

4343
/******** Send command ************/
44-
spi->txrx(cmd,NULL,MMC_CMD_SIZE);
45-
spi->txrx_byte(0xFF);
44+
spi.txrx(cmd,NULL,MMC_CMD_SIZE);
45+
spi.txrx_byte(0xFF);
4646

4747
/******** Get response ************/
4848
rxchar = wait_response(0, 0x80); /* Wait for byte with MSB == 0 */
4949
if (rxchar != 0)
5050
{
51-
spi->deselect();
51+
spi.deselect();
5252
return rxchar;
5353
}
5454

5555
rspdata[0]=rxchar;
56-
spi->txrx(NULL,rspdata+1,rsplength-1);
56+
spi.txrx(NULL,rspdata+1,rsplength-1);
5757

5858
return rxchar;
5959
}
@@ -71,8 +71,8 @@ uint8_t MMC::command(const uint8_t *cmd, uint8_t * rspdata, int rsplength)
7171

7272
/******** Data phase ************/
7373

74-
spi->deselect();
75-
spi->txrx_byte(0xFF);
74+
spi.deselect();
75+
spi.txrx_byte(0xFF);
7676

7777
return rxchar;
7878
};
@@ -90,15 +90,15 @@ uint8_t MMC::mmc_init(void)
9090
{
9191
int count;
9292

93-
spi->deselect();
94-
for (int i=0;i<10;i++) spi->txrx_byte(0xFF);
93+
spi.deselect();
94+
for (int i=0;i<10;i++) spi.txrx_byte(0xFF);
9595

9696
command(CMD0_GO_IDLE_STATE, mmc_response_buffer, 1);
9797

9898
count = 0;
9999
do
100100
{
101-
spi->txrx(CMD55_APP_CMD,NULL,MMC_CMD_SIZE);
101+
spi.txrx(CMD55_APP_CMD,NULL,MMC_CMD_SIZE);
102102
command(ACMD41_SD_SEND_OP_COND, mmc_response_buffer, 1);
103103
/* Here we can check response to identify SD cards */
104104
} while ((mmc_response_buffer[0] != 0) && (++count<10));

‎hardware/cores/stm32/MMC.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,13 @@
1111
class MMC
1212
{
1313
public:
14-
MMC(Spi * _spi){spi=_spi;};
14+
MMC(Spi & _spi):spi(_spi){};
1515
uint8_t wait_response(uint8_t response, uint8_t mask);
1616
uint8_t command(const unsigned char *cmd, uint8_t * rxdata, int rlength);
1717
uint8_t mmc_init(void);
1818

1919
private:
20-
Spi * spi;
20+
Spi & spi;
2121
uint8_t mmc_cmd_buffer[MMC_CMD_SIZE];
2222
uint8_t mmc_response_buffer[6];
2323
uint8_t command_response (const uint8_t *cmd, uint8_t * rspdata, int rsplength);

‎hardware/cores/stm32/pins_stm32.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,10 @@
2525
#ifndef Pins_STM32_h
2626
#define Pins_STM32_h
2727

28+
#if 0
2829
#include <stm32f10x_map.h>
2930
#include <stm32f10x_gpio.h>
31+
#endif
3032

3133
#define NOT_A_PIN 0
3234
#define NOT_A_PORT 0

‎hardware/cores/stm32/wiring.c

Lines changed: 7 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -31,9 +31,6 @@
3131
*/
3232

3333
#include "wiring_private.h"
34-
#include "stm32f10x_rcc.h"
35-
#include "stm32f10x_adc.h"
36-
#include "stm32f10x_flash.h"
3734

3835
/* Disable interrupts */
3936
#define DisableInterrups() __asm(" cpsid i\n")
@@ -120,36 +117,12 @@ void init()
120117
// work there
121118

122119
// Configure system clocks
123-
// 1. Clocking the controller from internal HSI RC (8 MHz)
124-
RCC_HSICmd(ENABLE);
125-
// wait until the HSI is ready
126-
while(RCC_GetFlagStatus(RCC_FLAG_HSIRDY) == RESET);
127-
RCC_SYSCLKConfig(RCC_SYSCLKSource_HSI);
128-
// Flash 2 wait state
129-
// *(vu32 *)0x40022000 = 0x12; /* FLASH_ACR */
130-
FLASH->ACR = FLASH_Latency_2 | FLASH_PrefetchBuffer_Enable;
131-
// 2. Enable ext. high frequency OSC
132-
RCC_HSEConfig(RCC_HSE_ON);
133-
// wait until the HSE is ready
134-
while(RCC_GetFlagStatus(RCC_FLAG_HSERDY) == RESET);
135-
// 3. Init PLL
136-
RCC_PLLConfig(RCC_PLLSource_HSE_Div1,RCC_PLLMul_9); // PLL = MCK = HCLK = 72MHz
137-
RCC_PLLCmd(ENABLE);
138-
// wait until the PLL is ready
139-
while(RCC_GetFlagStatus(RCC_FLAG_PLLRDY) == RESET);
140-
// 4. Set system clock divders
141-
RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5); // USBCLK = 48MHz
142-
RCC_PCLK2Config(RCC_HCLK_Div1); // PCLK2 = 72MHz
143-
RCC_PCLK1Config(RCC_HCLK_Div2); // PCLK1 = 36MHz
144-
RCC_ADCCLKConfig(RCC_PCLK2_Div8); // ADCCLK = 9MHz
145-
RCC_HCLKConfig(RCC_SYSCLK_Div1);
146-
// 5. Clock system from PLL
147-
RCC_SYSCLKConfig(RCC_SYSCLKSource_PLLCLK);
148-
120+
SystemInit ();
121+
149122
// Enable GPIO port clocks
150-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_AFIO, ENABLE);
123+
RCC->APB2ENR = RCC_APB2ENR_IOPAEN | RCC_APB2ENR_IOPBEN | RCC_APB2ENR_IOPCEN | RCC_APB2ENR_AFIOEN;
151124
// Enable timer clocks
152-
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM2 | RCC_APB1Periph_TIM4, ENABLE);
125+
RCC->APB1ENR = RCC_APB1ENR_TIM2EN | RCC_APB1ENR_TIM4EN;
153126
// Pin configurations and remappings
154127
/* Disable JTAG functionality */
155128
AFIO->MAPR = (AFIO->MAPR&~(7<<24))|(4<<24);
@@ -173,10 +146,9 @@ void init()
173146
// enable a2d conversions
174147

175148
/* Start peripherial clock and reset peripherial */
176-
RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE);
177-
RCC->APB2ENR |= RCC_APB2Periph_ADC1; /* ADC1EN */ /* bit 9 */
178-
RCC->APB2RSTR |= RCC_APB2Periph_ADC1; /* ADC1RST */ /* bit 9 */
179-
RCC->APB2RSTR &= ~RCC_APB2Periph_ADC1; /* ADC1RST */ /* bit 9 */
149+
RCC->APB2ENR = RCC_APB2ENR_ADC1EN; /* ADC1EN */ /* bit 9 */
150+
RCC->APB2RSTR |= RCC_APB2RSTR_ADC1RST; /* ADC1RST */ /* bit 9 */
151+
RCC->APB2RSTR &= ~RCC_APB2RSTR_ADC1RST; /* ADC1RST */ /* bit 9 */
180152

181153
/* Configure ADC */
182154
/* One channel single conversion mode, no DMA and no IRQ */

‎hardware/cores/stm32/wiring.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,8 +25,8 @@
2525
#ifndef Wiring_h
2626
#define Wiring_h
2727

28-
#include <stm32f10x_gpio.h>
29-
#include <stm32f10x_tim.h>
28+
//#include <stm32f10x_gpio.h>
29+
//#include <stm32f10x_tim.h>
3030
#include <unistd.h>
3131
#include <stdint.h>
3232
#include "binary.h"

‎hardware/cores/stm32/wiring_analog.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -24,8 +24,8 @@
2424

2525
#include "wiring_private.h"
2626
#include "pins_stm32.h"
27-
#include "stm32f10x_adc.h"
28-
#include "stm32f10x_tim.h"
27+
//#include "stm32f10x_adc.h"
28+
//#include "stm32f10x_tim.h"
2929

3030
#define ADC_SR_EOC (1<<1)
3131
#define ADC_CR1_DISCEN (1<<11)
@@ -65,7 +65,7 @@ void configTimerChannelPWM(TIM_TypeDef * TIM, uint8_t chn)
6565
/* Configure Output Compare */
6666
ccmr = *((uint32_t *)(&TIM->CCMR1)+(chn>>1));
6767
ccmr &= ~(0xFF<<(8*(chn&1)));
68-
ccmr |= ( (TIM_OCMode_PWM1 | TIM_OCPreload_Enable)<<(8*(chn&1)) );
68+
ccmr |= ( (TIM_CCMR_OCMode_PWM1 | TIM_CCMR_OCPreload_Enable)<<(8*(chn&1)) );
6969
*((uint32_t *)(&TIM->CCMR1)+(chn>>1)) = ccmr;
7070

7171
/* Output compare enable */

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