[go: up one dir, main page]
Wikipedia

Template:Features of AMD Processors with 3D Graphics: Difference between revisions

Browse history interactively
← Previous edit
Content deleted Content added
VisualWikitext
Correct
mNo edit summary
 
(19 intermediate revisions by 13 users not shown)
Line 1:
The following table shows features of [[Advanced Micro Devices|AMD]]'s processors with 3D graphics, including {{When pagename is
| List of AMD Processorsprocessors with 3D Graphicsgraphics = [[AcceleratedAMD processing unitAPU|APU]]s.
| other = [[AcceleratedAMD processing unitAPU|APU]]s (see also: [[List of AMD Processorsprocessors with 3D Graphicsgraphics]]).}}
{{navbar-table|Features of AMD Processors with 3D Graphics}}
{| class="wikitable" style="font-size: 85%; text-align: center"
Line 22:
|-
! {{rh}} rowspan=4 |Desktop
! {{rh}} class="table-rh" | Performance
! colspan=12 |
! rowspan=2 | [[List_of_AMD_accelerated_processing_units#"Raphael"_(2022)|Raphael]]
! rowspan="3" |[[List_of_AMD_accelerated_processing_units#"Phoenix"_(2023)|Phoenix]]
!
! colspan=9 rowspan=3 |
|-
Line 41:
! rowspan=2 | [[List_of_AMD_accelerated_processing_units#"Renoir"_(2020)|Renoir]]
! rowspan=2 | [[List_of_AMD_accelerated_processing_units#"Cezanne"_(2021)|Cezanne]]
 
!
 
!
Line 48 ⟶ 46:
|-
! {{rh}} | Entry
! colspan=3"2" |
|-
! {{rh}} | Basic
Line 78 ⟶ 76:
! rowspan=2 | [[List_of_AMD_accelerated_processing_units#"Raven_Ridge"_(2017)|Raven Ridge]]
! [[List_of_AMD_accelerated_processing_units#"Picasso"_(2019)_2|Picasso]]
! [[List_of_AMD_accelerated_processing_units#U|Renoir]]<br />[[List_of_AMD_accelerated_processing_units#"Lucienne"_(2021)|Lucienne]]
![[List_of_AMD_accelerated_processing_units#U_2|Cezanne]]<br />[[List_of_AMD_accelerated_processing_units#"Barceló"_(2022)|Barceló]]▼
 
▲![[List_of_AMD_accelerated_processing_units#U_2|Cezanne]]<br />[[List_of_AMD_accelerated_processing_units#"Barceló"_(2022)|Barceló]]
 
![[List_of_AMD_accelerated_processing_units#"Phoenix"_(2023)|Phoenix]]
|-
Line 107 ⟶ 103:
! [[List_of_AMD_accelerated_processing_units#"Bald_Eagle"_(2014)|Bald Eagle]]
!
! [[List_of_AMD_accelerated_processing_units#"Merlin_Falcon"_(2015%2C_SoC)|Merlin Falcon]],<br />[[List_of_AMD_accelerated_processing_units#I-Family:_"Brown_Falcon"_(2016,_SoC)|Brown Falcon]]
!
! [[List_of_AMD_accelerated_processing_units#V1000-Family:_"Great_Horned_Owl"_(2018,_SoC)|Great Horned Owl]]
Line 115 ⟶ 111:
! [[List_of_AMD_accelerated_processing_units#Brazos:_"Ontario"_and_"Zacate"_(2011)|Ontario, Zacate]]
! [[List_of_AMD_accelerated_processing_units#"Kabini"_(2013,_SoC)_2|Kabini]]
! [[List_of_AMD_accelerated_processing_units#"Steppe_Eagle"_(2014,_SoC)|Steppe Eagle]], [[List_of_AMD_accelerated_processing_units#"Crowned_Eagle"_(2014,_SoC)|Crowned Eagle]],<br /> [[List_of_AMD_accelerated_processing_units#LX-Family_(2016,_SoC)|LX-Family]]
!
! [[List_of_AMD_accelerated_processing_units#J-Family:_"Prairie_Falcon"_(2016,_SoC)|Prairie Falcon]]
Line 137 ⟶ 133:
| [[Zen 2]]
| [[Zen 3]]
| [[Zen 3|Zen 3+]]
| colspan=2 | [[Zen 4]]
| [[Bobcat (microarchitecture)|Bobcat]]
Line 148 ⟶ 144:
| "[[Zen 2|Zen 2+]]"
|-
| {{rh}} colspan=3 | [[Instruction set architecture|ISA]] || [[x86-64]] v1 || colspan=64 | [[x86-64]] v2 || colspan=57 | [[x86-64]] v3 || colspan=2 | [[x86-64]] v4 || [[x86-64]] v1 || colspan=43 | [[x86-64]] v2 || colspan=45 | [[x86-64]] v3
|- style="border-top:0.2em solid grey"
| {{rh}} rowspan=5 | [[Template:AMD CPU sockets|Socket]]
| {{rh}} rowspan=4 | Desktop
Line 157 ⟶ 153:
| {{n/a}}
| rowspan=3 colspan=9 {{n/a}}
 
|-
| {{rh}} | Mainstream
Line 163 ⟶ 158:
| colspan=6 | [[Socket AM4|AM4]]
| {{n/a}}
 
! {{n/a}}
|-
Line 190 ⟶ 184:
| colspan=2 | [[Socket FP6|FP6]]
| [[Socket FP7|FP7]]
| FL1
| {{dunno}}
| FP7 <br> FP7r2 <br> FP8
 
| {{dunno}}
| [[Socket FT1|FT1]]
Line 213 ⟶ 207:
| {{rh}} colspan=3 | [[Compute Express Link|CXL]] || colspan=14 {{n/a}}
| colspan=9 {{n/a}}
|- style="border-top:0.2em solid grey"
| {{rh}} colspan=3 | [[Semiconductor device fabrication|Fab.]] ([[Nanometre|nm]])
| colspan=3 | [[GlobalFoundries|GF]] [[32 nm process|32SHP]]<br />([[HKMG]] [[Silicon on insulator|SOI]])
| colspan=4 | GF [[32 nm process|28SHP]]<br />(HKMG bulk)
| GF [[14 nm process|14LPP]]<br />([[FinFET]] bulk)
| GF [[14 nm process|12LP]]<br />(FinFET bulk)
| colspan=2 | [[TSMC]] [[7 nm process|N7]]<br />(FinFET bulk)
| TSMC [[7 nm process|N6]]<br /> (FinFET bulk)
| {{nowrap|CCD: TSMC [[5 nm process|N5]]<br /> (FinFET bulk)}}<br /> {{nowrap|cIOD: TSMC [[7 nm process|N6]]<br /> (FinFET bulk)}}
| TSMC [[5 nm process|4nm]]<br /> (FinFET bulk)
| TSMC [[45 nm process|N40]]<br />(bulk)
| TSMC [[32 nm process|N28]]<br />(HKMG bulk)
| colspan=3 | GF 28SHP<br />(HKMG bulk)
| colspan=2 | GF [[14 nm process|14LPP]]<br />([[FinFET]] bulk)
| GF [[14 nm process|12LP]]<br />(FinFET bulk)
| TSMC [[7 nm process|N6]]<br /> (FinFET bulk)
|-
| {{rh}} colspan=3 | [[Die (integrated circuit)|Die]] area (mm<sup>2</sup>) || 228 || colspan=2 | 246 || colspan=2 | 245 || 245 || 250 || colspan=2 | 210<ref>{{cite web|title=The Mobile CPU Comparison Guide Rev. 13.0 Page 5 : AMD Mobile CPU Full List|url=https://www.techarp.com/guides/mobile-cpu-comparison-guide/5/ |access-date=13 December 2017|publisher=TechARP.com}}</ref> || 156
| 180 || 210 || |CCD: (2x) 70<br>cIOD: 122
| 178|| 75 {{nowrap|(+ 28 [[List of AMD chipsets#Fusion controller hubs (FCH)|FCH]])}} || colspan=2 | 107 || {{dunno}} || 125 || 149 || || ||~100
|-
| {{rh}} colspan=3 | Min [[Thermal Design Power|TDP]] (W) || 35 || colspan=4 | 17 || colspan=4 | 12 || colspan=2 | 10 || 15 || 10565 || 35 || 4.5 || 4 || 3.95 || 10 || colspan=3 | 6 || 12 || 8
|-
| {{rh}} colspan=3 | Max APU [[Thermal Design Power|TDP]] (W) || colspan=3 | 100 || colspan=2 | 95 || colspan=6 | 65 || 45 || 170 || 54 || 18 || colspan=5 | 25 || 6 || 54 || 15
Line 251 ⟶ 246:
| {{rh}} colspan=3 | Max [[thread (computing)|threads]] per CPU core || colspan=7 | 1 || colspan=7 | 2 || colspan=5 | 1 || colspan=4 | 2
|-
| {{rh}} colspan=3 | Integer pipeline structure || 3+3 || colspan=6 | 2+2 || colspan=2 | 4+2 || 4+2+1 || colspan=4 | 1+3+3+1+2 || colspan=4 | 1+1+1+1 || 2+2 || colspan=3 | 4+2 || colspan=1 | 4+2+1
|-
| {{rh}} colspan=3 | i386, i486, i586, CMOV, NOPL, i686, [[Physical_Address_Extension|PAE]], [[NX bit]], CMPXCHG16B, [[AMD-V]], [[Second_Level_Address_Translation#RVI|RVI]], [[Bit_Manipulation_Instruction_Sets#ABM_(Advanced_Bit_Manipulation)|ABM]], and 64-bit LAHF/SAHF || colspan=14 {{ya}}
| rowspan=1 colspan=9 {{ya}}
|-
| {{rh}} colspan=3 | [[IOMMU]]{{efn|name=iommubios|Requires firmware support.}} || rowspan=2 {{n/a}} || rowspan=1 colspan=13 | v2 || colspan=2 | v1 || colspan=7 | v2
|-
| {{rh}} colspan=3 | [[Bit_Manipulation_Instruction_Sets#BMI1_(Bit_Manipulation_Instruction_Set_1)|BMI1]], [[AES_instruction_set|AES-NI]], [[CLMUL]], and [[F16C]]
Line 266 ⟶ 261:
| colspan=4 {{n/a}} || colspan=5 {{ya}}
|-
| {{rh}} colspan=3 | [[AMD SME|SME]] {{efn|name=firmware|Requires firmware support.}}, [[TSME]] {{efn|name=firmware|Requires firmware support.}}, [[Intel_ADX|ADX]], [[Intel_SHA_extensions|SHA]], [[RDSEED]], [[Supervisor_Mode_Access_Prevention|SMAP]], [[Control_register#SMEP|SMEP]], XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO, and PTE Coalescing || colspan=7 {{n/a}} || colspan=7 {{ya}}
| rowspan=1 colspan=5 {{n/a}} || colspan=4 {{ya}}
|-
| {{rh}} colspan=3 | [[Second_Level_Address_Translation#Mode_Based_Execution_Control|GMET]], WBNOINVD, CLWB, QOS, PQE-BW, RDPID, RDPRU, and MCOMMIT || colspan=9 {{n/a}} || colspan=5 {{ya}}
| colspan=8 {{n/a}} || {{ya}}
 
|-
| {{rh}} colspan=3 | [[Memory_protection#Protection_keys|MPK]], {{nowrap|[[VAES]]}} || colspan=10 {{n/a}} || colspan=4 {{ya}}
Line 277 ⟶ 271:
|-
| {{rh}} colspan=3 | [[Software Guard Extensions|SGX]] || colspan=14 {{n/a}} || colspan=9 {{n/a}}
|- style="border-top:0.2em solid grey"
| {{rh}} colspan=3 | [[Floating-point unit|FPUs]] per [[Multi-core processor|core]] || 1 || colspan=6 | 0.5 || colspan=7 | 1 || colspan=4 | 1 || 0.5 || colspan=4 | 1
|-
Line 284 ⟶ 278:
| {{rh}} colspan=3 | FPU pipe width || colspan=9 | 128-bit || colspan=5 | 256-bit || 80-bit || colspan=7 | 128-bit || 256-bit
|-
| {{rh}} colspan=3 | CPU [[Instruction set|instruction set]] [[Single instruction, multiple data|SIMD]] level || [[SSE4a]]{{efn|name="sse4a"|No SSE4. No SSSE3.}} || colspan=4 | [[Advanced Vector Extensions|AVX]]
| colspan=7 | [[Advanced Vector Extensions#Advanced_Vector_Extensions_2|AVX2]] || colspan=2 | [[AVX-512]] || [[SSSE3]] || colspan=3 | [[Advanced Vector Extensions|AVX]] || colspan=5 | [[Advanced Vector Extensions#Advanced_Vector_Extensions_2|AVX2]]
|-
Line 303 ⟶ 297:
| {{rh}} colspan=3 | [[FMA3]] || colspan=13 {{ya}}
| colspan=5 {{ya}}
|- style="border-top:0.2em solid grey"
| {{rh}} colspan=3 | [[AMD XDNA]] || colspan=13 {{n/a}} || colspan=1 {{ya}}
| colspan=9 {{n/a}}
|- style="border-top:0.2em solid grey"
| {{rh}} colspan=3 | [[L1 cache|L1]] data cache per core (KiB) || 64 || colspan=4 | 16 || colspan=9 | 32 || colspan=9 | 32
|-
Line 324 ⟶ 318:
|colspan=3 | 4
| 8
|- style="border-top:0.2em solid grey"
| {{rh}} colspan=3 | [[L2 cache|L2 caches]]s per [[Multi-core processor|core]] || 1 || colspan=6 | 0.5 || colspan=7 | 1 || colspan=4 | 1 || 0.5 || colspan=4 | 1
|-
| {{rh}} colspan=3 | Max APU total L2 cache (MiB) || colspan=5 | 4 || colspan=4 | 2 || colspan=3 | 4 || 16 || || 1 || colspan=3 | 2 || colspan=3 | 1 || colspan=2 | 2
|-
| {{rh}} colspan=3 | L2 cache [[Cache placement policies#Set-associative_cache|associativity]] (ways) || colspan=7 | 16 || colspan=7 | 8 || colspan=5 | 16 || colspan=4 | 8
|- style="border-top:0.2em solid grey"
| {{rh}} colspan=3 | Max on--die [[L3 cache]] per CCX (MiB) || colspan=7 rowspan=8 {{n/a}} || colspan=3 | 4 || colspan=2 | 16 || 32 || || colspan=6 rowspan=8 {{n/a}} || colspan=4 | 4
|-
| {{rh}} colspan="3" | Max 3D V-Cache per CCD (MiB) || colspan=5 {{n/a}} || 64 || {{n/a}} || colspan=4 {{n/a}}
 
|-
Line 339 ⟶ 333:
 
|-
| {{rh}} colspan="3" | Max. total 3D V-Cache per APU (MiB) || colspan=5 {{n/a}} || 64 || {{n/a}} || colspan=4 {{n/a}}
 
|-
| {{rh}} colspan="3" | Max. board [[L3 cache]] per APU (MiB) || colspan=7 {{n/a}} || colspan=4 {{n/a}}
 
|-
| {{rh}} colspan=3 | Max total [[L3 cache]] per APU (MiB) || colspan=2 | 4 || 8 || colspan=2 | 16 || 128 || || colspan=4 | 4
Line 350 ⟶ 342:
|-
| {{rh}} colspan=3 | L3 cache scheme || colspan=7 | [[Victim cache|Victim]] || colspan=4 | [[Victim cache|Victim]]
|- style="border-top:0.2em solid grey"▼
 
▲|- style="border-top:0.2em solid grey"
| {{rh}} colspan="3" | Max. [[L4 cache]] || colspan="14" {{n/a}} || colspan=9 {{n/a}}
|- style="border-top:0.2em solid grey"▼
 
| {{rh}} colspan=3 | Max stock [[Dynamic random-access memory|DRAM]] support || colspan=2 | [[DDR3 SDRAM|DDR3]]-1866 || colspan=3 | DDR3-2133 || DDR3-2133, [[DDR4 SDRAM|DDR4]]-2400 || DDR4-2400 || colspan=2 | DDR4-2933 || colspan=2 | DDR4-3200, [[LPDDR#LPDDR4|LPDDR4]]-4266 || [[DDR5 SDRAM|DDR5]]-4800, [[LPDDR#LPDDR5|LPDDR5]]-6400 || [[DDR5 SDRAM|DDR5]]-5200 || [[DDR5 SDRAM|DDR5]]-5600, [[LPDDR#LPDDR5x|LPDDR5x]]-7500 || [[DDR3L|DDR3L]]-1333 || DDR3L-1600 || colspan=2 | DDR3L-1866 || DDR3-1866, [[DDR4 SDRAM|DDR4]]-2400 || DDR4-2400 || DDR4-1600 || DDR4-3200 || LPDDR5-5500▼
▲|- style="border-top:0.2em solid grey"
▲| {{rh}} colspan=3 | Max stock [[Dynamic random-access memory|DRAM]] support || colspan=2 | [[DDR3 SDRAM|DDR3]]-1866 || colspan=3 | DDR3-2133 || DDR3-2133, [[DDR4 SDRAM|DDR4]]-2400 || DDR4-2400 || colspan=2 | DDR4-2933 || colspan=2 | DDR4-3200, [[LPDDR#LPDDR4|LPDDR4]]-4266 || [[DDR5 SDRAM|DDR5]]-4800, [[LPDDR#LPDDR5|LPDDR5]]-6400 || [[DDR5 SDRAM|DDR5]]-5200 || [[DDR5 SDRAM|DDR5]]-5600, [[LPDDR#LPDDR5x|LPDDR5x]]-7500 || [[DDR3L|DDR3L]]-1333 || DDR3L-1600 || colspan=2 | DDR3L-1866 || DDR3-1866, [[DDR4 SDRAM|DDR4]]-2400 || DDR4-2400 || DDR4-1600 || DDR4-3200 || LPDDR5-5500
|-
| {{rh}} colspan=3 | Max [[Dynamic random-access memory|DRAM]] channels per APU || colspan=14 | 2 || colspan=5 | 1 || 2 || 1 || colspan=2 | 2
Line 361 ⟶ 351:
| {{rh}} colspan=3 | Max stock [[Dynamic random-access memory|DRAM]] [[Bandwidth (computing)|bandwidth]] (GB/s) per APU || colspan=2 | 29.866 || colspan=3 | 34.132 || colspan=2 | 38.400 || colspan=2 | 46.932 || colspan=2 | 68.256 || 102.400 || 83.200 || 120.000
| 10.666 || 12.800 || colspan=2 | 14.933 || 19.200 || 38.400 || 12.800 || 51.200 || 88.000
|- style="border-top:0.2em solid grey"
| {{rh}} colspan=3 | GPU [[microarchitecture]] || [[TeraScale (microarchitecture)#TeraScale 2 "Evergreen"-family|TeraScale 2 (VLIW5)]] || colspan=2 | [[TeraScale (microarchitecture)#TeraScale 3 "Northern Islands"-family|TeraScale 3 (VLIW4)]] || colspan=2 | [[Graphics Core Next#GCN 2nd generation|GCN 2nd gen]] || colspan=2 | [[Graphics Core Next#GCN 3rd generation|GCN 3rd gen]] || colspan=4 | [[Graphics Core Next#GCN 5th generation|GCN 5th gen]]<ref name="Vega codenames">{{cite web |url=http://videocardz.com/62250/amd-vega10-and-vega11-gpus-spotted-in-opencl-driver/ |title=AMD VEGA10 and VEGA11 GPUs spotted in OpenCL driver |publisher=VideoCardz.com |access-date=6 June 2017}}</ref> || colspan=2 | [[RDNA (microarchitecture)#RDNA 2|RDNA 2nd gen]] || [[RDNA (microarchitecture)#RDNA 3|RDNA 3rd gen]] || [[TeraScale (microarchitecture)#TeraScale 2 "Evergreen"-family|TeraScale 2 (VLIW5)]] || colspan=3 | [[Graphics Core Next#GCN 2nd generation|GCN 2nd gen]] || [[Graphics Core Next#GCN 3rd generation|GCN 3rd gen]]<ref name="Vega codenames" /> || colspan=3 | [[Graphics Core Next#GCN 5th generation|GCN 5th gen]] || [[RDNA (microarchitecture)#RDNA 2|RDNA 2nd gen]]
|-
| {{rh}} colspan=3 | GPU [[Instruction set|instruction set]] || colspan=3 | [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan=8 | [[Graphics Core Next#Instruction set|GCN instruction set]] || colspan=3 | [[RDNA (microarchitecture)#Instruction set|RDNA instruction set]] || [[TeraScale (microarchitecture)|TeraScale]] instruction set || colspan=7 | [[Graphics Core Next#Instruction set|GCN instruction set]] || [[RDNA (microarchitecture)#Instruction set|RDNA instruction set]]
|-
| {{rh}} colspan=3 | Max stock GPU base clock (MHz) || 600 || 800 || 844 || colspan=2 | 866 || colspan=2 | 1108 || 1250 || 1400 || colspan=2 | 2100 || 2400 || 400 ||
Line 371 ⟶ 361:
| {{rh}} colspan=3 | Max stock GPU base [[GFLOPS]]{{efn|name="SFLOPS"}} || 480 || 614.4 || 648.1 || colspan=2 | 886.7 || colspan=2 | 1134.5 || 1760 || 1971.2 || colspan=2 | 2150.4 || 3686.4 || 102.4 ||
| 86 || {{dunno}} || {{dunno}} || {{dunno}} || 345.6 || 460.8 || 230.4 || 1331.2 || 486.4
|- style="border-top:0.2em solid grey"
| rowspan=2 {{rh}} colspan=3 | 3D engine{{efn|[[Unified shader model|Unified shaders]] : [[texture mapping unit]]s : [[render output unit]]s}} || Up to 400:20:8 || colspan=2 | Up to 384:24:6 || colspan=4 | Up to 512:32:8 || colspan=2 | Up to 704:44:16<ref>{{cite news |last1=Cutress |first1=Ian |title=Zen Cores and Vega: Ryzen APUs for AM4 – AMD Tech Day at CES: 2018 Roadmap Revealed, with Ryzen APUs, Zen+ on 12nm, Vega on 7nm |url=https://www.anandtech.com/show/12233/amd-tech-day-at-ces-2018-roadmap-revealed-with-ryzen-apus-zen-on-12nm-vega-on-7nm/3 |access-date=7 February 2018 |publisher=Anandtech |date=1 February 2018}}</ref> || colspan=2 | Up to 512:32:8 || 768:48:8 || 128:?8:?4 || || 80:8:4 || colspan=3 | 128:8:4 || Up to 192:12:8 || Up to 192:12:4 || 192:12:4 || Up to 512:?:? || 128:?:?
|-
| colspan=3 | IOMMUv1 || colspan=11 | [[Heterogeneous Memory Management|IOMMUv2]] || colspan=2 | IOMMUv1 || colspan=2 {{dunno}} || colspan=5 | IOMMUv2
|- style="border-top:0.2em solid grey"
| {{rh}} colspan=3 | Video decoder || colspan=3 | [[Unified Video Decoder#UVD 3|UVD 3.0]] || colspan=2 | [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || colspan=2 | [[Unified Video Decoder#UVD 6|UVD 6.0]] || rowspan=2 colspan=2 | [[Video Core Next|VCN]] 1.0<ref>{{cite news |last1=Larabel |first1=Michael |title=Radeon VCN Encode Support Lands in Mesa 17.4 Git |url=https://www.phoronix.com/scan.php?page=news_item&px=Radeon-VCN-Encode-Lands |access-date=20 November 2017 |publisher=Phoronix |date=17 November 2017}}</ref> || rowspan="2" | VCN 2.1<ref name="wccftechCezanne">{{cite web|last=|first=|date=Aug 12, 2021|title=AMD Ryzen 5000G ‘Cezanne’ APU Gets First High-Res Die Shots, 10.7 Billion Transistors In A 180mm2 Package|url=https://wccftech.com/amd-ryzen-5000g-cezanne-apu-first-high-res-die-shots-10-7-billion-transistors/|url-status=live|access-date=August 25, 2021|website=wccftech|quote=}}</ref>
| rowspan="2" | VCN 2.2<ref name="wccftechCezanne" /> || colspan=2 rowspan=2 | VCN 3.1 || rowspan=2 {{dunno}} || [[Unified Video Decoder#UVD 3|UVD 3.0]] || [[Unified Video Decoder#UVD 4|UVD 4.0]] || [[Unified Video Decoder#UVD 4.2|UVD 4.2]] || [[Unified Video Decoder#UVD 6|UVD 6.0]] || [[Unified Video Decoder#UVD 6|UVD 6.3]] || rowspan=2 colspan=3 | [[Video Core Next|VCN 1.0]] || rowspan=2 | VCN 3.1
|-
| {{rh}} colspan=3 | Video encoder || {{Nn/Aa}} || colspan=2 | [[Video Coding Engine#VCE 1.0|VCE 1.0]] || colspan=2 | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan=2 | [[Video Coding Engine#VCE 3.0|VCE 3.1]] || {{Nn/Aa}} || colspan=2 | [[Video Coding Engine#VCE 2.0|VCE 2.0]] || colspan=2 | [[Video Coding Engine#VCE 3.0|VCE 3.1]]
|-
| {{rh}} colspan=3 |AMD Fluid Motion
Line 390 ⟶ 380:
|-
| {{rh}} colspan=3 | GPU power saving || [[AMD PowerPlay|PowerPlay]] || colspan=13 | [[AMD PowerTune|PowerTune]] || [[AMD PowerPlay|PowerPlay]] || colspan=8 | [[AMD PowerTune|PowerTune]]<ref>{{citation |url=http://meseec.ce.rit.edu/551-projects/fall2014/3-4.pdf |title=AMD's Graphics Core Next (GCN) Architecture |author=Tony Chen |author2=Jason Greaves |work=AMD |access-date=13 August 2016}}</ref>
|-
| {{rh}} colspan=3 | [[AMD TrueAudio|TrueAudio]] || colspan=3 rowspan=2 {{Nn/Aa}} || colspan=7 {{ya}}<ref>{{cite web |url=http://semiaccurate.com/2014/01/15/technical-look-amds-kaveri-architecture/ |title=A technical look at AMD's Kaveri architecture |publisher=Semi Accurate |access-date=6 July 2014}}</ref> || colspan=4 {{dunno}}
| rowspan=2 {{Nn/Aa}} || colspan=8 {{ya}}
|-
| {{rh}} colspan=3 | [[FreeSync]] || colspan=11 style="background:#DFD;" | 1<br />2
| colspan=88 style="background:#DFD;" | 1<br />2
|-
| {{rh}} colspan=3 | [[HDCP]]{{efn|name="DRM"}} || colspan=3 {{dunno}} || colspan=4 | 1.4 || colspan=4 | 2.2 || colspan=3 | 2.3 || {{dunno}} || colspan=4 | 1.4 || colspan=3 | 2.2 || 2.3
Line 401 ⟶ 391:
| {{rh}} colspan=3 | [[PlayReady]]{{efn|name="DRM"}} || colspan=7 {{n/a}} || colspan=7 | 3.0 not yet || colspan=5 {{n/a}} || colspan=4 | 3.0 not yet
|-
| {{rh}} colspan=3 | [[AMD Eyefinity|Supported displays]]{{efn|To feed more than two displays, the additional panels must have native [[DisplayPort]] support.<ref>{{cite web | url=http://support.amd.com/en-us/search/faq/154 | title=How do I connect three or More Monitors to an AMD Radeon™ HD 5000, HD 6000, and HD 7000 Series Graphics Card? | publisher=AMD | access-date=8 December 2014}}</ref> Alternatively active DisplayPort-to-DVI/HDMI/VGA adapters can be employed.}} || 2–3 || colspan=4 | 2–4 || colspan=2 | 3 || colspan=2 | 3 (desktop)<br />4 (mobile, embedded) || colspan=5 | 4 || colspan=4 | 2 || 3 || 4 || || colspan=2 | 4
|- style="border-top:0.2em solid grey"
| {{rh}} colspan=3 | <code>/drm/radeon</code>{{efn|name="drm"}}<ref>{{cite web |url=http://airlied.livejournal.com/68805.html |title=DisplayPort supported by KMS driver mainlined into Linux kernel 2.6.33 |date=26 November 2009 |access-date=16 January 2016 |last1=Airlie |first1=David}}</ref><ref name="Radeon Feature Matrix">{{cite web |url=http://xorg.freedesktop.org/wiki/RadeonFeature/ |title=Radeon feature matrix |work=[[freedesktop.org]] |access-date=10 January 2016}}</ref> || colspan=6 {{ya}} || colspan=8 {{Nn/Aa}}
| colspan=4 {{ya}} || colspan=5 {{Nn/Aa}}
|-
| {{rh}} colspan=3 | <code>/drm/amdgpu</code>{{efn|name="drm"}}<ref>{{cite web |url=http://www.x.org/wiki/Events/XDC2015/Program/deucher_zhou_amdgpu.pdf |title=XDC2015: AMDGPU |date=16 September 2015 |last1=Deucher |first1=Alexander |access-date=16 January 2016}}</ref> || colspan=3 {{Nn/Aa}} || colspan=11 {{ya}}<ref name="amdgpu_1.2">{{cite web |url=https://lists.x.org/archives/xorg-announce/2016-November/002741.html |title=[ANNOUNCE] xf86-video-amdgpu 1.2.0 |author=Michel Dänzer |work=lists.x.org |date=17 November 2016}}</ref>
| {{Nn/Aa}} || colspan=8 {{ya}}<ref name="amdgpu_1.2"/>
|}
{{noteslist|refs=
Line 417 ⟶ 407:
 
== See also ==
*<!-- [[Template:AMD x86 CPU features]] was deleted per oldid=1142398499#Template:AMD_x86_CPU_features -->
* [[Template:AMD GPU features]]
 
Retrieved from "https://en.wikipedia.org/wiki/Template:Features_of_AMD_Processors_with_3D_Graphics"