VDD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than VDD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption." />
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Boosted Voltage Scheme with Active Body-Biasing Control on PD-SOI for Ultra Low Voltage Operation

Masaaki IIJIMA
Masayuki KITAMURA
Masahiro NUMA
Akira TADA
Takashi IPPOSHI
Shigeto MAEGAWA

Publication
IEICE TRANSACTIONS on Electronics   Vol.E90-C    No.4    pp.666-674
Publication Date: 2007/04/01
Online ISSN: 1745-1353
DOI: 10.1093/ietele/e90-c.4.666
Print ISSN: 0916-8516
Type of Manuscript: Special Section PAPER (Special Section on Low-Power, High-Speed LSIs and Related Technologies)
Category: Digital
Keyword: 
low power design,  PD-SOI,  body-bias,  pass-transistor logic,  circuit simulation,  SRAM,  

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Summary: 
In this paper, we propose an Active Body-biasing Controlled (ABC)-Bootstrap PTL (Pass-Transistor Logic) on PD-SOI for ultra low power design. Although simply lowering the supply voltage (VDD) causes a lack of driving power, our boosted voltage scheme employing a strong capacitive coupling with ABC-SOI improves a driving power and allows lower voltage operation. We also present an SOI-SRAM design boosting the word line (WL) voltage higher than VDD in short transition time without dual power supply rails. Simulation results have shown improvement in both the delay time and power consumption.