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ORCIDYuriy M. Greshishchev
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2020 – today
- 2023
[j6]Yuriy M. Greshishchev
:
Guest Editorial IEEE 2022 BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium. IEEE J. Solid State Circuits 58(9): 2405-2406 (2023)
2010 – 2019
- 2019
- [c10]Sebastien Blais, Yuriy M. Greshishchev, Peter Schvan, Ian Betty, Douglas McGhan:
Coherent Transceiver for High Speed Optical Communications: Opportunities and Challenges. BCICTS 2019: 1-6 - [c9]Yuriy M. Greshishchev, Tingjun Wen, Naim Ben-Hamida, Jorge Aguirre, Sadok Aouini, Marinette Besson, Robert Gibbins, Young Gouk Cho, Jerry Lam, Douglas McPherson, Mahdi Parvizi:
A 60 GS/s 8-b DAC with > 29.5dB SINAD up to Nyquist frequency in 7nm FinFET CMOS. BCICTS 2019: 1-4 - 2011
- [c8]Yuriy M. Greshishchev, Daniel Pollex, Shing-Chi Wang, Marinette Besson, Philip Flemeke, Stefan Szilagyi, Jorge Aguirre, Chris Falt, Naim Ben-Hamida, Robert Gibbins, Peter Schvan:
A 56GS/S 6b DAC in 65nm CMOS with 256×6b memory. ISSCC 2011: 194-196 - 2010
- [c7]Yuriy M. Greshishchev, Jorge Aguirre, Marinette Besson, Robert Gibbins, Chris Falt, Philip Flemke, Naim Ben-Hamida, Daniel Pollex, Peter Schvan, Shing-Chi Wang:
A 40GS/s 6b ADC in 65nm CMOS. ISSCC 2010: 390-391 - [c6]Yuriy M. Greshishchev, Franz Dielacher, Michael Flynn, Donhee Ham, Naresh R. Shanbhag, Takuji Yamamoto:
Transceiver circuits for optical communications. ISSCC 2010: 514-515
2000 – 2009
- 2009
- [c5]Naim Ben-Hamida, John Sitch, Philip Flemke, Daniel Pollex, Peter Schvan, Yuriy M. Greshishchev, Shing-Chi Wang, Chris Falt:
Clock recovery for a 40 Gb/s QPSK optical receiver. ICECS 2009: 695-698 - 2008
- [c4]Yuriy M. Greshishchev, Takuji Yamamoto, Naresh R. Shanbhag:
Trends and Challenges in Optical Communications Front-End. ISSCC 2008: 394-395 - [c3]Peter Schvan, Jérôme Bach, Chris Falt, Philip Flemke, Robert Gibbins, Yuriy M. Greshishchev, Naim Ben-Hamida, Daniel Pollex, John Sitch, Shing-Chi Wang, John Wolczanski:
A 24GS/s 6b ADC in 90nm CMOS. ISSCC 2008: 544-545 - 2007
- [c2]Sung Min Park, Yuriy M. Greshishchev:
Optical Communications. ISSCC 2007: 40-41 - 2005
- [j5]Axel Thomsen, Jacques Christophe Rudell, Yuriy M. Greshishchev, J. E. D. Hurwitz:
Introduction to the Special Issue on the 2005 IEEE International Solid-State Circuits Conference. IEEE J. Solid State Circuits 40(12): 2359-2363 (2005) - 2000
- [j4]Yuriy M. Greshishchev, Peter Schvan:
SiGe clock and data recovery IC with linear-type PLL for 10-Gb/s SONET application. IEEE J. Solid State Circuits 35(9): 1353-1359 (2000) - [j3]Yuriy M. Greshishchev, Peter Schvan, Jonathan L. Showell, Mu-Liang Xu, Jugnu J. Ojha, Jonathan E. Rogers:
A fully integrated SiGe receiver IC for 10-Gb/s data rate. IEEE J. Solid State Circuits 35(12): 1949-1957 (2000)
1990 – 1999
- 1999
- [j2]Yuriy M. Greshishchev, Peter Schvan:
A 60-dB gain, 55-dB dynamic range, 10-Gb/s broad-band SiGe HBT limiting amplifier. IEEE J. Solid State Circuits 34(12): 1914-1920 (1999) - 1997
- [j1]Tirdad Sowlati, Yuriy M. Greshishchev, C. André T. Salama:
Phase-correcting feedback system for class E power amplifier. IEEE J. Solid State Circuits 32(4): 544-549 (1997) - 1995
- [c1]Tirdad Sowlati, Yuriy M. Greshishchev, C. André T. Salama, Gord Rabjohn, John Sitch:
Linear transmitter design using high efficiency Class E power amplifier. PIMRC 1995: 1233
Coauthor Index
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