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2010 – 2019
- 2019
[i1]Fantine Huot, Yi-Fan Chen, Robert G. Clapp, Carlos Boneti, John R. Anderson:
High-resolution imaging on TPUs. CoRR abs/1912.08063 (2019)- 2013
- [j2]Alessandro Morari, Carlos Boneti, Francisco J. Cazorla
, Roberto Gioiosa, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
SMT Malleability in IBM POWER5 and POWER6 Processors. IEEE Trans. Computers 62(4): 813-826 (2013) - 2011
- [j1]Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Characterizing Power and Temperature Behavior of POWER6-Based System. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 228-241 (2011) - 2010
- [c5]Víctor Jiménez, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero, Carlos Boneti, Eren Kursun, Chen-Yong Cher, Canturk Isci, Alper Buyuktosunoglu, Pradip Bose:
Power and thermal characterization of POWER6 system. PACT 2010: 7-18
2000 – 2009
- 2009
- [b1]Carlos Boneti:
Exploring coordinated software and hardware support for hardware resource allocation. Polytechnic University of Catalonia, Spain, 2009 - 2008
- [c4]Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Mateo Valero:
Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation. ARCS 2008: 173-187 - [c3]Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Julita Corbalán, Jesús Labarta, Mateo Valero:
Balancing HPC applications through smart allocation of resources in MT processors. IPDPS 2008: 1-12 - [c2]Carlos Boneti, Francisco J. Cazorla, Roberto Gioiosa, Alper Buyuktosunoglu, Chen-Yong Cher, Mateo Valero:
Software-Controlled Priority Characterization of POWER5 Processor. ISCA 2008: 415-426 - [c1]Carlos Boneti, Roberto Gioiosa, Francisco J. Cazorla, Mateo Valero:
A dynamic scheduler for balancing HPC applications. SC 2008: 41
Coauthor Index
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