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2020 – today
- 2024
[j31]JongHyun Ko, Dongseok Kwon, Joon Hwang, Kyu-Ho Lee, Seongbin Oh, Jeonghyun Kim, Jiseong Im, Ryun-Han Koo, Jae-Joon Kim, Jong-Ho Lee
:
SNNSim: Investigation and Optimization of Large-Scale Analog Spiking Neural Networks Based on Flash Memory Devices. Adv. Intell. Syst. 6(4) (2024)- [j30]Sungju Ryu, Jaeyong Jang, Youngtaek Oh, Jae-Joon Kim:
Mobileware: Distributed Architecture With Channel Stationary Dataflow for MobileNet Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(9): 2661-2673 (2024) - [c59]Eunhwan Kim, Hyunmyung Oh, Jehun Lee, Jihoon Park, Myeongeun Kwon, Jae-Joon Kim:
A 10T2C Capacitive SRAM-based Computing-In-Memory Macro with Array-Embedded DAC and Shift-and-Add Functions. CICC 2024: 1-2 - [c58]Hyunsung Yoon, Jae-Joon Kim:
Fused Sampling and Grouping with Search Space Reduction for Efficient Point Cloud Acceleration. DAC 2024: 194:1-194:6 - [c57]Munhyeon Kim, Jae-Joon Kim:
4-Transistor Ternary Content Addressable Memory Cell Design using Stacked Hybrid IGZO/Si Transistors. DAC 2024: 335:1-335:6 - [c56]Jaeyong Jang, Yulhwa Kim, Juheun Lee, Jae-Joon Kim:
FIGNA: Integer Unit-Based Accelerator Design for FP-INT GEMM Preserving Numerical Accuracy. HPCA 2024: 760-773 - [c55]Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim:
SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks. ICML 2024 - [i12]Hyesung Jeon, Yulhwa Kim, Jae-Joon Kim:
L4Q: Parameter Efficient Quantization-Aware Training on Large Language Models via LoRA-wise LSQ. CoRR abs/2402.04902 (2024) - [i11]Jiwon Song, Kyungseok Oh, Taesu Kim, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim:
SLEB: Streamlining LLMs through Redundancy Verification and Elimination of Transformer Blocks. CoRR abs/2402.09025 (2024) - [i10]Dongwon Jo, Taesu Kim, Yulhwa Kim, Jae-Joon Kim:
Mixture of Scales: Memory-Efficient Token-Adaptive Binarization for Large Language Models. CoRR abs/2406.12311 (2024) - 2023
- [j29]Wonjun Shin, Kyung Kyu Min, Jong-Ho Bae, Jaehyeon Kim, Ryun-Han Koo, Dongseok Kwon, Jae-Joon Kim, Daewoong Kwon, Jong-Ho Lee:
1/f Noise in Synaptic Ferroelectric Tunnel Junction: Impact on Convolutional Neural Network. Adv. Intell. Syst. 5(6) (2023) - [j28]Taesu Kim, Daehyun Ahn, Dongsoo Lee, Jae-Joon Kim:
V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(10): 3327-3337 (2023) - [j27]Eunhwan Kim, Hyunmyung Oh, Nameun Kang, Jihoon Park, Jae-Joon Kim:
A Capacitive Computing-In-Memory Circuit With Low Input Loading SRAM Bitcell and Adjustable ADC Input Range. IEEE Trans. Circuits Syst. II Express Briefs 70(9): 3268-3272 (2023) - [j26]Sungju Ryu, Youngtaek Oh, Jae-Joon Kim:
Binaryware: A High-Performance Digital Hardware Accelerator for Binary Neural Networks. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2137-2141 (2023) - [c54]Inhwan Lee, Eunhwan Kim, Nameun Kang, Hyunmyung Oh, Jae-Joon Kim:
In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time. DAC 2023: 1-6 - [c53]Hyunsung Yoon, Jae-Joon Kim:
Efficient Sampling and Grouping Acceleration for Point Cloud Deep Learning via Single Coordinate Comparison. ICCAD 2023: 1-9 - [c52]Changhun Lee, Hyungjun Kim, Eunhyeok Park, Jae-Joon Kim:
INSTA-BNN: Binary Neural Network with INSTAnce-aware Threshold. ICCV 2023: 17279-17288 - [c51]Yulhwa Kim, Jaeyong Jang, Jehun Lee, Jihoon Park, Jeonghoon Kim, Byeongwook Kim, Baeseong Park, Se Jung Kwon, Dongsoo Lee, Jae-Joon Kim:
Winning Both the Accuracy of Floating Point Activation and the Simplicity of Integer Arithmetic. ICLR 2023 - [c50]Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Taesu Kim, Daehyun Ahn, Hyungjun Kim, Jae-Joon Kim:
Leveraging Early-Stage Robustness in Diffusion Models for Efficient and High-Quality Image Synthesis. NeurIPS 2023 - [c49]Daehyun Ahn, Hyungjun Kim, Taesu Kim, Eunhyeok Park, Jae-Joon Kim:
Searching for Robust Binary Neural Networks via Bimodal Parameter Perturbation. WACV 2023: 2409-2418 - [i9]Jiwoong Choi, Minkyu Kim, Daehyun Ahn, Taesu Kim, Yulhwa Kim, Dongwon Jo, Hyesung Jeon, Jae-Joon Kim, Hyungjun Kim:
Squeezing Large-Scale Diffusion Models for Mobile. CoRR abs/2307.01193 (2023) - 2022
- [j25]Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim:
Extreme Partial-Sum Quantization for Analog Computing-In-Memory Neural Network Accelerators. ACM J. Emerg. Technol. Comput. Syst. 18(4): 75:1-75:19 (2022) - [j24]Sungju Ryu, Hyungjun Kim, Wooseok Yi, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim:
BitBlade: Energy-Efficient Variable Bit-Precision Hardware Accelerator for Quantized Neural Networks. IEEE J. Solid State Circuits 57(6): 1924-1935 (2022) - [j23]Sehun Park, Jae-Joon Kim, Jaeha Kung:
AutoRelax: HW-SW Co-Optimization for Efficient SpGEMM Operations With Automated Relaxation in Deep Learning. IEEE Trans. Emerg. Top. Comput. 10(3): 1428-1442 (2022) - [c48]Nameun Kang, Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim:
TAIM: ternary activation in-memory computing hardware with 6T SRAM array. DAC 2022: 1081-1086 - [c47]Naebeom Park, Daehyun Ahn, Jae-Joon Kim:
Workload-Balanced Graph Attention Network Accelerator with Top-K Aggregation Candidates. ICCAD 2022: 39:1-39:9 - [i8]Changhun Lee, Hyungjun Kim, Eunhyeok Park, Jae-Joon Kim:
INSTA-BNN: Binary Neural Network with INSTAnce-aware Threshold. CoRR abs/2204.07439 (2022) - 2021
- [j22]Daehyun Ahn, Hyunmyung Oh, Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim:
Maximizing Parallel Activation of Word-Lines in MRAM-Based Binary Neural Network Accelerators. IEEE Access 9: 141961-141969 (2021) - [j21]Sungju Ryu, Jongeun Koo, Wook Kim, Yonghwan Kim, Jae-Joon Kim:
Variation-Tolerant Elastic Clock Scheme for Low-Voltage Operations. IEEE J. Solid State Circuits 56(7): 2245-2255 (2021) - [j20]Naebeom Park, Sungju Ryu, Jaeha Kung, Jae-Joon Kim:
High-throughput Near-Memory Processing on CNNs with 3D HBM-like Memory. ACM Trans. Design Autom. Electr. Syst. 26(6): 48:1-48:20 (2021) - [c46]Hyunmyung Oh, Hyungjun Kim, Nameun Kang, Yulhwa Kim, Jihoon Park, Jae-Joon Kim:
Single RRAM Cell-based In-Memory Accelerator Architecture for Binary Neural Networks. AICAS 2021: 1-4 - [c45]Hyunmyung Oh, Hyungjun Kim, Daehyun Ahn, Jihoon Park, Yulhwa Kim, Inhwan Lee, Jae-Joon Kim:
Energy-efficient charge sharing-based 8T2C SRAM in-memory accelerator for binary neural networks in 28nm CMOS. A-SSCC 2021: 1-3 - [c44]Hyungjun Kim, Jihoon Park, Changhun Lee, Jae-Joon Kim:
Improving Accuracy of Binary Neural Networks Using Unbalanced Activation Distribution. CVPR 2021: 7862-7871 - [c43]Sungju Ryu, Youngtaek Oh, Taesu Kim, Daehyun Ahn, Jae-Joon Kim:
SPRITE: Sparsity-Aware Neural Processing Unit with Constant Probability of Index-Matching. DATE 2021: 663-666 - [c42]Yulhwa Kim, Hyungjun Kim, Jihoon Park, Hyunmyung Oh, Jae-Joon Kim:
Mapping Binary ResNets on Computing-In-Memory Hardware with Low-bit ADCs. DATE 2021: 856-861 - [c41]Sungju Ryu, Youngtaek Oh, Jae-Joon Kim:
Mobileware: A High-Performance MobileNet Accelerator with Channel Stationary Dataflow. ICCAD 2021: 1-9 - 2020
- [j19]Junki Park, Wooseok Yi, Daehyun Ahn, Jaeha Kung, Jae-Joon Kim:
Balancing Computation Loads and Optimizing Input Vector Loading in LSTM Accelerators. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(9): 1889-1901 (2020) - [j18]Wooseok Yi, Junki Park, Jae-Joon Kim:
GeCo: Classification Restricted Boltzmann Machine Hardware for On-Chip Semisupervised Learning and Bayesian Inference. IEEE Trans. Neural Networks Learn. Syst. 31(1): 53-65 (2020) - [c40]Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jongeun Koo, Eunhwan Kim, Yulhwa Kim, Taesu Kim, Jae-Joon Kim:
A 44.1TOPS/W Precision-Scalable Accelerator for Quantized Neural Networks in 28nm CMOS. CICC 2020: 1-4 - [c39]Haerang Choi, Yosep Lee, Jae-Joon Kim, Sungjoo Yoo:
A Novel In-DRAM Accelerator Architecture for Binary Neural Network. COOL CHIPS 2020: 1-3 - [c38]Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim:
Algorithm/Hardware Co-Design for In-Memory Neural Network Computing with Minimal Peripheral Circuit Overhead. DAC 2020: 1-6 - [c37]Taesu Kim, Daehyun Ahn, Jae-Joon Kim:
V-LSTM: An Efficient LSTM Accelerator Using Fixed Nonzero-Ratio Viterbi-Based Pruning. FPGA 2020: 326 - [c36]Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim:
Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution Regularization. ICCAD 2020: 94:1-94:9 - [c35]Hyungjun Kim, Kyungsu Kim, Jinseok Kim, Jae-Joon Kim:
BinaryDuo: Reducing Gradient Mismatch in Binary Activation Network by Coupling Binary Activations. ICLR 2020 - [c34]Naebeom Park, Yulhwa Kim, Daehyun Ahn, Taesu Kim, Jae-Joon Kim:
Time-step interleaved weight reuse for LSTM neural network computing. ISLPED 2020: 13-18 - [c33]Junki Park, Hyunsung Yoon, Daehyun Ahn, Jungwook Choi, Jae-Joon Kim:
OPTIMUS: OPTImized matrix MUltiplication Structure for Transformer neural network accelerator. MLSys 2020 - [c32]Jinseok Kim, Kyungsu Kim, Jae-Joon Kim:
Unifying Activation- and Timing-based Learning Rules for Spiking Neural Networks. NeurIPS 2020 - [i7]Hyungjun Kim, Kyungsu Kim, Jinseok Kim, Jae-Joon Kim:
BinaryDuo: Reducing Gradient Mismatch in Binary Activation Network by Coupling Binary Activations. CoRR abs/2002.06517 (2020) - [i6]Jinseok Kim, Kyungsu Kim, Jae-Joon Kim:
Unifying Activation- and Timing-based Learning Rules for Spiking Neural Networks. CoRR abs/2006.02642 (2020) - [i5]Hyungjun Kim, Jihoon Park, Changhun Lee, Jae-Joon Kim:
Improving Accuracy of Binary Neural Networks using Unbalanced Activation Distribution. CoRR abs/2012.00938 (2020)
2010 – 2019
- 2019
- [j17]Jongeun Koo, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim:
Low-overhead, one-cycle timing-error detection and correction technique for flip-flop based pipelines. IEICE Electron. Express 16(11): 20190180 (2019) - [j16]Shihui Yin, Jae-sun Seo, Yulhwa Kim, Xu Han, Hugh J. Barnaby, Shimeng Yu, Yandong Luo, Wangxin He, Xiaoyu Sun, Jae-Joon Kim:
Monolithically Integrated RRAM- and CMOS-Based In-Memory Computing Optimizations for Efficient Deep Learning. IEEE Micro 39(6): 54-63 (2019) - [j15]Sungju Ryu, Naebeom Park, Jae-Joon Kim:
Feedforward-Cutset-Free Pipelined Multiply-Accumulate Unit for the Machine Learning Accelerator. IEEE Trans. Very Large Scale Integr. Syst. 27(1): 138-146 (2019) - [c31]Hyungjun Kim, Yulhwa Kim, Jae-Joon Kim:
In-memory batch-normalization for resistive memory based binary neural network hardware. ASP-DAC 2019: 645-650 - [c30]Jongeun Koo, Eunhwan Kim, Seunghyun Yoo, Taesu Kim, Sungju Ryu, Jae-Joon Kim:
Configurable BCAM/TCAM Based on 6T SRAM Bit Cell and Enhanced Match Line Clamping. A-SSCC 2019: 223-226 - [c29]Jongeun Koo, Jinseok Kim, Sungju Ryu, Chulsoo Kim, Jae-Joon Kim:
Area-Efficient Transposable 6T SRAM for Fast Online Learning in Neuromorphic Processors. CICC 2019: 1-4 - [c28]Sungju Ryu, Hyungjun Kim, Wooseok Yi, Jae-Joon Kim:
BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise Summation. DAC 2019: 84 - [c27]Jaeha Kung, Junki Park, Sehun Park, Jae-Joon Kim:
Peregrine: A Flexible Hardware Accelerator for LSTM with Limited Synaptic Connection Patterns. DAC 2019: 209 - [c26]Wooseok Yi, Yulhwa Kim, Jae-Joon Kim:
Effect of Device Variation on Mapping Binary Neural Network to Memristor Crossbar Array. DATE 2019: 320-323 - [c25]Daehyun Ahn, Dongsoo Lee, Taesu Kim, Jae-Joon Kim:
Double Viterbi: Weight Encoding for High Compression Ratio and Fast On-Chip Reconstruction for Deep Neural Network. ICLR (Poster) 2019 - [c24]Jinseok Kim, Jongeun Koo, Taesu Kim, Yulhwa Kim, Hyungjun Kim, Seunghyun Yoo, Jae-Joon Kim:
Area-Efficient and Variation-Tolerant In-Memory BNN Computing using 6T SRAM Array. VLSI Circuits 2019: 118- - [i4]Hyungjun Kim, Yulhwa Kim, Sungju Ryu, Jae-Joon Kim:
BitSplit-Net: Multi-bit Deep Neural Network with Bitwise Activation Function. CoRR abs/1903.09807 (2019) - [i3]Hyungjun Kim, Malte J. Rasch, Tayfun Gokmen, Takashi Ando, Hiroyuki Miyazoe, Jae-Joon Kim, John Rozen, Seyoung Kim:
Zero-shifting Technique for Deep Neural Network Training on Resistive Cross-point Arrays. CoRR abs/1907.10228 (2019) - 2018
- [j14]Hyungjun Kim, Taesu Kim, Jinseok Kim, Jae-Joon Kim:
Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics. ACM J. Emerg. Technol. Comput. Syst. 14(2): 15:1-15:17 (2018) - [c23]Junki Park, Jaeha Kung, Wooseok Yi, Jae-Joon Kim:
Maximizing system performance by balancing computation loads in LSTM accelerators. DATE 2018: 7-12 - [c22]Dongsoo Lee, Daehyun Ahn, Taesu Kim, Pierce I-Jen Chuang, Jae-Joon Kim:
Viterbi-based Pruning for Sparse Matrix with Fixed and High Index Compression Ratio. ICLR (Poster) 2018 - [c21]Jinseok Kim, Yulhwa Kim, Sungho Kim, Jae-Joon Kim:
Compact Convolution Mapping on Neuromorphic Hardware using Axonal Delay. ISLPED 2018: 3:1-3:6 - [c20]Yulhwa Kim, Hyungjun Kim, Daehyun Ahn, Jae-Joon Kim:
Input-Splitting of Large Neural Networks for Power-Efficient Accelerator with Resistive Crossbar Memory Array. ISLPED 2018: 41:1-41:6 - [i2]Yulhwa Kim, Hyungjun Kim, Jae-Joon Kim:
Neural Network-Hardware Co-design for Scalable RRAM-based BNN Accelerators. CoRR abs/1811.02187 (2018) - 2017
- [c19]Sungju Ryu, Jongeun Koo, Jae-Joon Kim:
Low design overhead timing error correction scheme for elastic clock methodology. ISLPED 2017: 1-6 - [c18]Eunhwan Kim, Minah Lee, Jae-Joon Kim:
8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistors. ISSCC 2017: 144-145 - [c17]Wooseok Yi, Junki Park, Jae-Joon Kim:
GeCo: classification restricted Boltzmann machine hardware for on-chip learning. RSP 2017: 30-35 - [i1]Hyungjun Kim, Taesu Kim, Jinseok Kim, Jae-Joon Kim:
Deep Neural Network Optimized to Resistive Memory with Nonlinear Current-Voltage Characteristics. CoRR abs/1703.10642 (2017) - 2016
- [j13]Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin:
One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 600-612 (2016) - [c16]Jongeun Koo, Eunwoo Song, Eunhyeok Park, Dongyoung Kim, Junki Park, Sungju Ryu, Sungjoo Yoo, Jae-Joon Kim:
Area-efficient one-cycle correction scheme for timing errors in flip-flop based pipelines. A-SSCC 2016: 137-140 - [e1]Youngsoo Shin, Chi-Ying Tsui, Jae-Joon Kim, Kiyoung Choi, Ricardo Reis:
VLSI-SoC: Design for Reliability, Security, and Low Power - 23rd IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, Daejeon, Korea, October 5-7, 2015, Revised Selected Papers. IFIP Advances in Information and Communication Technology 483, Springer 2016, ISBN 978-3-319-46096-3 [contents] - 2015
- [j12]Insup Shin, Jae-Joon Kim, Youngsoo Shin:
Aggressive Voltage Scaling Through Fast Correction of Multiple Errors With Seamless Pipeline Operation. IEEE Trans. Circuits Syst. I Regul. Pap. 62-I(2): 468-477 (2015) - 2014
- [c15]Insup Shin, Jae-Joon Kim, Youngsoo Shin:
Power minimization of pipeline architecture through 1-cycle error correction and voltage scaling. ASP-DAC 2014: 179-184 - [c14]Hayoung Kim, Dongyoung Kim, Jae-Joon Kim, Sungjoo Yoo, Sunggu Lee:
Coarse-grained Bubble Razor to exploit the potential of two-phase transparent latch designs. DATE 2014: 1-6 - 2013
- [j11]Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown:
Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection. IEEE Trans. Very Large Scale Integr. Syst. 21(9): 1683-1692 (2013) - [c13]Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin:
A pipeline architecture with 1-cycle timing error correction for low voltage operations. ISLPED 2013: 199-204 - 2012
- [c12]Xiuyuan Bi, Hai Li, Jae-Joon Kim:
Analysis and Optimization of Thermal Effect on STT-RAM Based 3-D Stacked Cache Design. ISVLSI 2012: 374-379 - 2011
- [j10]Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang:
SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage. IEEE Trans. Very Large Scale Integr. Syst. 19(1): 24-32 (2011) - [j9]Ik Joon Chang, Jae-Joon Kim, Keejong Kim, Kaushik Roy:
Robust Level Converter for Sub-Threshold/Super-Threshold Operation: 100 mV to 2.5 V. IEEE Trans. Very Large Scale Integr. Syst. 19(8): 1429-1437 (2011) - [c11]Sang Phill Park, Soo Youn Kim, Dongsoo Lee, Jae-Joon Kim, W. Paul Griffin, Kaushik Roy:
Column-selection-enabled 8T SRAM array with ~1R/1W multi-port operation for DVFS-enabled processors. ISLPED 2011: 303-308 - 2010
- [j8]Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy:
Self-Repairing SRAM Using On-Chip Detection and Compensation. IEEE Trans. Very Large Scale Integr. Syst. 18(1): 75-84 (2010) - [c10]Jae-Joon Kim, Rahul M. Rao, Keunwoo Kim:
Technology-circuit co-design of asymmetric SRAM cells for read stability improvement. CICC 2010: 1-4
2000 – 2009
- 2009
- [j7]Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS. IEEE J. Solid State Circuits 44(2): 650-658 (2009) - [j6]Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim:
A Local Random Variability Detector With Complete Digital On-Chip Measurement Circuitry. IEEE J. Solid State Circuits 44(9): 2616-2623 (2009) - [j5]Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang:
Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectron. Reliab. 49(6): 642-649 (2009) - 2008
- [c9]Saibal Mukhopadhyay, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang:
Capacitive coupling based transient negative bit-line voltage (Tran-NBL) scheme for improving write-ability of SRAM design in nanometer technologies. ISCAS 2008: 384-387 - [c8]Ik Joon Chang, Jae-Joon Kim, Sang Phill Park, Kaushik Roy:
A 32kb 10T Subthreshold SRAM Array with Bit-Interleaving and Differential Read Scheme in 90nm CMOS. ISSCC 2008: 388-389 - [c7]Rahul M. Rao, Keith A. Jenkins, Jae-Joon Kim:
A Completely Digital On-Chip Circuit for Local-Random-Variability Measurement. ISSCC 2008: 412-413 - [c6]Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy:
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design 2008: 125-130 - [c5]Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown:
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit. VLSI Design 2008: 143-149 - [c4]Niladri Narayan Mojumder, Saibal Mukhopadhyay, Jae-Joon Kim, Ching-Te Chuang, Kaushik Roy:
Design and Analysis of a Self-Repairing SRAM with On-Chip Monitor and Compensation Circuitry. VTS 2008: 101-106 - 2007
- [j4]Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy:
Estimation of gate-to-channel tunneling current in ultra-thin oxide sub-50nm double gate devices. Microelectron. J. 38(8-9): 931-941 (2007) - 2006
- [j3]Chris Hyung-Il Kim, Jae-Joon Kim, Ik-Joon Chang, Kaushik Roy:
PVT-aware leakage reduction for on-die caches with improved read stability. IEEE J. Solid State Circuits 41(1): 170-178 (2006) - [j2]Jae-Joon Kim, Kaushik Roy:
A Leakage-Tolerant Low-Swing Circuit Style in Partially Depleted Silicon-on-Insulator CMOS Technologies. IEEE Trans. Very Large Scale Integr. Syst. 14(5): 549-552 (2006) - [c3]Ik Joon Chang, Jae-Joon Kim, Kaushik Roy:
Robust level converter design for sub-threshold logic. ISLPED 2006: 14-19 - 2005
- [j1]Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations. IEEE Trans. Very Large Scale Integr. Syst. 13(3): 349-357 (2005) - [c2]Saibal Mukhopadhyay, Keunwoo Kim, Jae-Joon Kim, Shih-Hsien Lo, Rajiv V. Joshi, Ching-Te Chuang, Kaushik Roy:
Modeling and Analysis of Gate Leakage in Ultra-thin Oxide Sub-50nm Double Gate Devices and Circuits. ISQED 2005: 410-415 - 2003
- [c1]Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy:
A forward body-biased low-leakage SRAM cache: device and architecture considerations. ISLPED 2003: 6-9
Coauthor Index
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