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ORCIDSebastian Hoyos
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2020 – today
- 2024
[j42]Il-Min Yi
, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo:
A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET. IEEE J. Solid State Circuits 59(9): 2948-2959 (2024)- [j41]Edoardo Bonizzoni, Sebastian Hoyos, Antonio Liscidini:
Guest Editorial Special Issue on the 2024 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2503 (2024) - [j40]Haotian Zhao, Julian Camilo Gomez Diaz, Sebastian Hoyos:
Multi-Channel Nonlinearity Mitigation Using Machine Learning Algorithms. IEEE Trans. Mob. Comput. 23(4): 2535-2550 (2024) - [c31]Haotian Zhao, Sebastian Hoyos:
Multi-Channel Nonlinearity Mitigation Using Neural-Network-Based Feedback Cancellation with Channel Decision Passing Algorithm. MWSCAS 2024: 286-290 - [c30]Gijin Park, Srujan Kumar Kaile, Il-Min Yi, Sebastian Hoyos, Samuel Palermo:
Comparisons of Metastability Impact in Time-Domain and Asynchronous SAR ADCs for Serial I/O Receivers. MWSCAS 2024: 1106-1110 - 2023
- [j39]Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, Il-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo:
A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET. IEEE J. Solid State Circuits 58(3): 662-676 (2023) - [j38]Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, Il-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo:
A 38-GS/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET. IEEE J. Solid State Circuits 58(8): 2300-2313 (2023) - [j37]Edoardo Bonizzoni, Sebastian Hoyos:
Guest Editorial Special Issue on the 2023 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs 70(5): 1673 (2023) - [j36]Edoardo Bonizzoni, Sebastian Hoyos:
Guest Editorial Special Issue on the 2023 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs 70(10): 3726 (2023) - [c29]Il-Min Yi, Srujan Kumar Kaile, Yuanming Zhu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo:
A 50Gb/s DAC-Based Multicarrier Polar Transmitter in 22nm FinFET. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j35]Haotian Zhao, Julian Camilo Gomez Diaz, Sebastian Hoyos:
Multi-Channel Receiver Nonlinearity Cancellation Using Channel Speculation Passing Algorithm. IEEE Trans. Circuits Syst. II Express Briefs 69(2): 599-603 (2022) - [j34]Julian Camilo Gomez Diaz, Haotian Zhao, Yuanming Zhu, Samuel Palermo, Sebastian Hoyos:
Recurrent Neural Network Equalization for Wireline Communication Systems. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2116-2120 (2022) - [j33]Edoardo Bonizzoni, Sebastian Hoyos:
Special Issue on the 2022 IEEE International Symposium on Circuits and Systems. IEEE Trans. Circuits Syst. II Express Briefs 69(5): 2393 (2022) - [j32]Edoardo Bonizzoni, Sebastian Hoyos:
Guest Editorial Special Issue on the 2022 ISICAS: A CAS Journal Track Symposium. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 3972 (2022) - [c28]Yuanming Zhu, Julian Camilo Gomez Diaz, Srujan Kumar Kaile, Il-Min Yi, Tong Liu, Sebastian Hoyos, Samuel Palermo:
A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET. CICC 2022: 1-2 - [c27]Yuanming Zhu, Tong Liu, Srujan Kumar Kaile, Shiva Kiran, Il-Min Yi, Ruida Liu, Julian Camilo Gomez Diaz, Sebastian Hoyos, Samuel Palermo:
A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET. CICC 2022: 1-2 - 2020
- [j31]Amir Tofighi Zavareh, Sebastian Hoyos:
Kalman-Based Real-Time Functional Decomposition for the Spectral Calibration in Swept Source Optical Coherence Tomography. IEEE Trans. Biomed. Circuits Syst. 14(2): 257-273 (2020) - [c26]Yuanming Zhu, Shengchang Cai, Shiva Kiran, Yang-Hang Fan, Po-Hsuan Chang, Sebastian Hoyos, Samuel Palermo:
A 1.5GS/s 8b Pipelined-SAR ADC with Output Level Shifting Settling Technique in 14nm CMOS. CICC 2020: 1-4
2010 – 2019
- 2019
- [j30]Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo:
A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. IEEE J. Solid State Circuits 54(3): 659-671 (2019) - [c25]Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo:
A 32 Gb/s ADC-Based PAM-4 Receiver with 2-bit/Stage SAR ADC and Partially-Unrolled DFE. CICC 2019: 1-4 - [c24]Julian Camilo Gomez Diaz, Amir Tofighi Zavareh, Lester Boampong, Sebastian Hoyos:
Blocker-Tolerant RF-to-Digital Linearization With a Very Nonlinear Auxiliary Path. MWSCAS 2019: 548-551 - [c23]Julian Camilo Gomez Diaz, Shiva Kiran, Samuel Palermo, Sebastian Hoyos:
Jitter-Robust Multicarrier ADC-Based Serial Link Receiver Architecture : (Invited Special Session Paper). MWSCAS 2019: 1151-1154 - 2018
- [c22]Amir Tofighi Zavareh, Sebastian Hoyos:
The Spectral Calibration of Swept-Source Optical Coherence Tomography Systems Using Unscented Kalman Filter. BioCAS 2018: 1-4 - [c21]Shiva Kiran, Shengchang Cai, Ying Luo, Sebastian Hoyos, Samuel Palermo:
A 32 Gb/s ADC-based PAM-4 receiver with 2-bit/stage SAR ADC and partially-unrolled DFE. CICC 2018: 1-4 - 2017
- [j29]Shengchang Cai, Ehsan Zhian Tabasy, Ayman Shafik, Shiva Kiran, Sebastian Hoyos, Samuel Palermo:
A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS. IEEE J. Solid State Circuits 52(8): 2168-2179 (2017) - [j28]Jun Zhou, Amir Tofighi Zavareh, Robin Gupta, Liang Liu, Zhongfeng Wang, Brian M. Sadler, José Silva-Martínez, Sebastian Hoyos:
Compressed Level Crossing Sampling for Ultra-Low Power IoT Devices. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2495-2507 (2017) - [c20]Amir Tofighi Zavareh, Oscar Barajas, Sebastian Hoyos:
An efficient estimation algorithm for the calibration of low-cost SS-OCT systems. ISBI 2017: 1169-1172 - [c19]Oscar Barajas, Amir Tofighi Zavareh, Sebastian Hoyos:
Towards an on-chip signal processing solution for the online calibration of SS-OCT systems. ISCAS 2017: 1-4 - 2016
- [j27]Samuel Palermo, Sebastian Hoyos, Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Shiva Kiran, Keytaek Lee:
CMOS ADC-based receivers for high-speed electrical and optical links. IEEE Commun. Mag. 54(10): 168-175 (2016) - [j26]Haoyu Qian, Qiyuan Liu, José Silva-Martínez, Sebastian Hoyos:
A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS. IEEE J. Solid State Circuits 51(3): 587-597 (2016) - [j25]Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Keytaek Lee, Sebastian Hoyos, Samuel Palermo:
A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization. IEEE J. Solid State Circuits 51(3): 671-685 (2016) - [c18]Amir Tofighi Zavareh, Oscar Barajas, Michael Serafino, Javier A. Jo, Brian E. Applegate, Brian M. Sadler, Sebastian Hoyos:
A novel continuous time ternary encoding based SS-OCT calibration. BioCAS 2016: 5-8 - [c17]Jun Zhou, Zhongfeng Wang, Sebastian Hoyos:
Compressed Power Spectral Density Estimation via Group-Based Total Variation Minimization. SiPS 2016: 7-10 - 2015
- [j24]Hyung-Joon Jeon, José Silva-Martínez, Sebastian Hoyos:
A Process-Variation Resilient Current Mode Logic With Simultaneous Regulations for Time Constant, Voltage Swing, Level Shifting, and DC Gain Using Time-Reference-Based Adaptive Biasing Chain. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 198-202 (2015) - [c16]Ayman Shafik, Ehsan Zhian Tabasy, Shengchang Cai, Keytaek Lee, Sebastian Hoyos, Samuel Palermo:
3.6 A 10Gb/s hybrid ADC-based receiver with embedded 3-tap analog FFE and dynamically-enabled digital equalization in 65nm CMOS. ISSCC 2015: 1-3 - [c15]Shengchang Cai, Ehsan Zhian Tabasy, Ayman Shafik, Shiva Kiran, Sebastian Hoyos, Samuel Palermo:
A 25GS/s 6b TI binary search ADC with soft-decision selection in 65nm CMOS. VLSIC 2015: 158- - 2014
- [j23]Ehsan Zhian Tabasy, Ayman Shafik, Keytaek Lee, Sebastian Hoyos, Samuel Palermo:
A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications. IEEE J. Solid State Circuits 49(11): 2560-2574 (2014) - [c14]Shiva Kiran, Sebastian Hoyos, Samuel Palermo:
A single parity check forward error correction method for high speed I/O. GlobalSIP 2014: 652-655 - 2013
- [j22]Ehsan Zhian Tabasy, Ayman Shafik, Shan Huang, Noah Hae-Woong Yang, Sebastian Hoyos, Samuel Palermo:
A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS. IEEE J. Solid State Circuits 48(8): 1885-1897 (2013) - [c13]Jun Zhou, Yong He, Mohan Chirala, Brian M. Sadler, Sebastian Hoyos:
Compressed Digital Beamformer with asynchronous sampling for ultrasound imaging. ICASSP 2013: 1056-1060 - [c12]Jun Zhou, Sebastian Hoyos:
Asynchronous Binary Compressive Sensing for Wireless Body Sensor Networks. MSN 2013: 121-126 - 2012
- [j21]Jun Zhou, Mario A. Ramirez, Samuel Palermo, Sebastian Hoyos:
Digital-Assisted Asynchronous Compressive Sensing Front-End. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(3): 482-492 (2012) - [j20]Xi Chen, Ehab Ahmed Sobhy, Zhuizhuan Yu, Sebastian Hoyos, José Silva-Martínez, Samuel Palermo, Brian M. Sadler:
A Sub-Nyquist Rate Compressive Sensing Data Acquisition Front-End. IEEE J. Emerg. Sel. Topics Circuits Syst. 2(3): 542-551 (2012) - [j19]Krishna Pentakota, Mario A. Ramirez, Sebastian Hoyos:
Least mean squared Background Calibration for OFDM Multichannel Receivers. J. Circuits Syst. Comput. 21(1) (2012) - [j18]Zhuizhuan Yu, Jun Zhou, Mario A. Ramirez, Sebastian Hoyos, Brian M. Sadler:
The impact of ADC nonlinearity in a mixed-signal compressive sensing system for frequency-domain sparse signals. Phys. Commun. 5(2): 196-207 (2012) - [j17]Ramy Saad, Diego Luis Aristizábal-Ramirez, Sebastian Hoyos:
Sensitivity Analysis of Continuous-Time Δ Σ ADCs to Out-of-Band Blockers in Future SAW-Less Multi-Standard Wireless Receivers. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(9): 1894-1905 (2012) - [j16]Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic:
A 15 MHz to 600 MHz, 20 mW, 0.38 mm2 Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 564-568 (2012) - [c11]Ehsan Zhian Tabasy, Ayman Shafik, S. Huang, N. Yang, Sebastian Hoyos, Samuel Palermo:
A 6b 1.6GS/s ADC with redundant cycle 1-tap embedded DFE in 90nm CMOS. CICC 2012: 1-4 - 2011
- [j15]Ehab Ahmed Sobhy, Srikanth Pentakota, Zhuizhuan Yu, Sebastian Hoyos:
Analytical framework and bandwidth optimisation of orthogonal frequency division multiplexing low-order multi-channel filter-bank receivers for achieving sampling clock-jitter robustness. IET Circuits Devices Syst. 5(5): 360-364 (2011) - [j14]Sebastian Hoyos, Srikanth Pentakota, Zhuizhuan Yu, Ehab Sobhy Abdel Ghany, Xi Chen, Ramy Saad, Samuel Palermo, José Silva-Martínez:
Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(2): 253-263 (2011) - [j13]Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler, José Silva-Martínez:
A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(3): 507-520 (2011) - [j12]Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler, José Silva-Martínez:
Corrections to "A Sub-Nyquist Rate Sampling Receiver Exploiting Compressive Sensing". IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(11): 2801 (2011) - [c10]Ramy Saad, Sebastian Hoyos:
Sensitivity analysis of pulse-width jitter induced noise in continuous-time delta-sigma modulators to out-of-band blockers in wireless receivers. ISCAS 2011: 1636-1639 - 2010
- [j11]Zhuizhuan Yu, Xi Chen, Sebastian Hoyos, Brian M. Sadler, Jingxuan Gong, Chengliang Qian:
Mixed-Signal Parallel Compressive Spectrum Sensing for Cognitive Radios. Int. J. Digit. Multim. Broadcast. 2010: 730509:1-730509:10 (2010) - [j10]Cho-Ying Lu, Jose Fabian Silva-Rivas, Praveena Kode, José Silva-Martínez, Sebastian Hoyos:
A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth. IEEE J. Solid State Circuits 45(6): 1122-1136 (2010) - [j9]Ehab Ahmed Sobhy, Sebastian Hoyos:
A Multiphase Multipath Technique With Digital Phase Shifters for Harmonic Distortion Cancellation. IEEE Trans. Circuits Syst. II Express Briefs 57-II(12): 921-925 (2010)
2000 – 2009
- 2009
- [c9]Yung-Chung Lo, Hsien-Pu Chen, José Silva-Martínez, Sebastian Hoyos:
A 1.8V, sub-mW, over 100% locking range, divide-by-3 and 7 complementary-injection-locked 4 GHz frequency divider. CICC 2009: 259-262 - [c8]Zhuizhuan Yu, Sebastian Hoyos:
Compressive Spectrum Sensing Front-ends for Cognitive Radios. SMC 2009: 1899-1994 - 2008
- [j8]Pradeep Kotte Prakasam, Mandar Kulkarni, Xi Chen, Zhuizhuan Yu, Sebastian Hoyos, José Silva-Martínez, Edgar Sánchez-Sinencio:
Applications of Multipath Transform-Domain Charge-Sampling Wide-Band Receivers. IEEE Trans. Circuits Syst. II Express Briefs 55-II(4): 309-313 (2008) - [c7]Cheongyuen W. Tsang, Yun Chiu, Johan P. Vanderhaegen, Sebastian Hoyos, Charles Chen, Robert W. Brodersen, Borivoje Nikolic:
Background ADC calibration in digital domain. CICC 2008: 301-304 - [c6]Sebastian Hoyos, Cheongyuen W. Tsang, Johan P. Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic:
A 15 MHz - 600 MHz, 20 mW, 0.38 mm2, fast coarse locking digital DLL in 0.13μm CMOS. ESSCIRC 2008: 90-93 - [c5]Zhuizhuan Yu, Sebastian Hoyos, Brian M. Sadler:
Mixed-signal parallel compressed sensing and reception for cognitive radio. ICASSP 2008: 3861-3864 - 2007
- [j7]Sebastian Hoyos, Brian M. Sadler:
UWB Mixed-Signal Transform-Domain Direct-Sequence Receiver. IEEE Trans. Wirel. Commun. 6(8): 3038-3046 (2007) - 2006
- [j6]Sebastian Hoyos, Brian M. Sadler, Gonzalo R. Arce:
Broadband multicarrier communication receiver based on analog to digital conversion in the frequency domain. IEEE Trans. Wirel. Commun. 5(3): 652-661 (2006) - 2005
- [j5]Sebastian Hoyos, Jan Bacca Rodríguez, Gonzalo R. Arce:
Spectral design of weighted median Filters: A general iterative approach. IEEE Trans. Signal Process. 53(3): 1045-1056 (2005) - [j4]Sebastian Hoyos, Brian M. Sadler:
Ultra-wideband analog-to-digital conversion via signal expansion. IEEE Trans. Veh. Technol. 54(5): 1609-1622 (2005) - [j3]Sebastian Hoyos, Brian M. Sadler, Gonzalo R. Arce:
Monobit digital receivers for ultrawideband communications. IEEE Trans. Wirel. Commun. 4(4): 1337-1344 (2005) - [c4]Sebastian Hoyos, Brian M. Sadler, Gonzalo R. Arce:
Ultra-wideband multicarrier communication receiver based on analog to digital conversion in the frequency domain. WCNC 2005: 782-787 - 2004
- [j2]Sebastian Hoyos, Jorge A. García, Gonzalo R. Arce:
Mixed-signal equalization architectures for printed circuit board channels. IEEE Trans. Circuits Syst. I Regul. Pap. 51-I(2): 264-274 (2004) - [j1]Sebastian Hoyos, Yinbo Li, Jan Bacca Rodríguez, Gonzalo R. Arce:
Weighted median filters admitting complex-valued weights and their optimization. IEEE Trans. Signal Process. 52(10): 2776-2787 (2004) - [c3]Sebastian Hoyos, Brian M. Sadler, Gonzalo R. Arce:
High-speed A/D conversion for ultra-wideband signals based on signal projection over basis functions. ICASSP (4) 2004: 537-540 - [c2]Jan Bacca Rodríguez, Sebastian Hoyos, Yinbo Li, Gonzalo R. Arce:
Weighted median based filters for the complex domain. ICASSP (2) 2004: 909-912 - 2002
- [c1]Sebastian Hoyos, Jorge A. García, Gonzalo R. Arce:
Mixed-signal equalization architectures for printed circuit board channels. ICASSP 2002: 3768-3771
Coauthor Index
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