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ORCIDRuzica Jevtic
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2020 – today
- 2025
[j12]Pablo Pérez-Tirador, Madhav P. Desai, Alejandro Rodriguez, Elena Berral, Teresa Romero, Gabriel Caffarena, Ruzica Jevtic:
Side-channel attacks and countermeasures for heart rate retrieval from ECG characterization device. Int. J. Inf. Sec. 24(1): 8 (2025)- 2022
- [j11]Ruzica Jevtic
, Mariano García Otero:
Methodology for Complete Decorrelation of Power Supply EM Side-Channel Signal and Sensitive Data. IEEE Trans. Circuits Syst. II Express Briefs 69(4): 2256-2260 (2022) - [c11]Ruzica Jevtic, Pablo Pérez-Tirador, Carmen Cabezaolias, Pablo Carnero, Gabriel Caffarena:
Side-channel Attack Countermeasure Based on Power Supply Modulation. EUSIPCO 2022: 618-622 - 2021
- [j10]Ruzica Jevtic, Marko Ylitolva, Clara Calonge, Martti Ojanen, Tero Säntti, Lauri Koskinen:
EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation. IEEE Trans. Very Large Scale Integr. Syst. 29(6): 1061-1072 (2021)
2010 – 2019
- 2018
- [c10]Ruzica Jevtic, Marko Ylitolva, Lauri Koskinen:
Reconfigurable Switched Capacitor DC-DC Converter for Improved Security in IoT Devices. PATMOS 2018: 243-247 - 2016
- [j9]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Steven Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V Vector Processor With Simultaneous-Switching Switched-Capacitor DC-DC Converters in 28 nm FDSOI. IEEE J. Solid State Circuits 51(4): 930-942 (2016) - [j8]Yunsup Lee, Andrew Waterman, Henry Cook, Brian Zimmer, Ben Keller, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Rimas Avizienis, Brian C. Richards, Jonathan Bachrach, David A. Patterson, Elad Alon, Bora Nikolic, Krste Asanovic:
An Agile Approach to Building RISC-V Microprocessors. IEEE Micro 36(2): 8-20 (2016) - 2015
- [j7]Ruzica Jevtic, Hanh-Phuc Le, Milovan Blagojevic, Stevo Bailey, Krste Asanovic, Elad Alon, Borivoje Nikolic:
Per-Core DVFS With Switched-Capacitor Converters for Energy Efficiency in Manycore Processors. IEEE Trans. Very Large Scale Integr. Syst. 23(4): 723-730 (2015) - [c9]Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic:
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. Hot Chips Symposium 2015: 1-45 - [c8]Fernando Cardes, Ruzica Jevtic, Luis Hernández, Andreas Wiesbauer, Dietmar Sträußnigg, Richard Gaggl:
A MEMS microphone interface based on a CMOS LC oscillator and a digital sigma-delta modulator. ISCAS 2015: 2233-2236 - [c7]Brian Zimmer, Yunsup Lee, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Hanh-Phuc Le, Po-Hung Chen, Nicholas Sutardja, Rimas Avizienis, Andrew Waterman, Brian C. Richards, Philippe Flatresse, Elad Alon, Krste Asanovic, Borivoje Nikolic:
A RISC-V vector processor with tightly-integrated switched-capacitor DC-DC converters in 28nm FDSOI. VLSIC 2015: 316- - [c6]Matthew J. Turnquist, Markus Hiienkari, Jani Mäkipää, Ruzica Jevtic, Elina Pohjalainen, Tanja Kallio, Lauri Koskinen:
Fully integrated DC-DC converter and a 0.4V 32-bit CPU with timing-error prevention supplied from a prototype 1.55V Li-ion battery. VLSIC 2015: 320- - 2014
- [j6]Pablo Barrio, Carlos Carreras, Juan A. López, Óscar Robles, Ruzica Jevtic, Roberto Sierra:
Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes. J. Syst. Archit. 60(7): 579-591 (2014) - [j5]Bojan Jovanovic, Ruzica Jevtic, Carlos Carreras:
Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits. IEEE Trans. Ind. Informatics 10(1): 393-398 (2014) - 2012
- [j4]Ruzica Jevtic, Carlos Carreras:
A complete dynamic power estimation model for data-paths in FPGA DSP designs. Integr. 45(2): 172-185 (2012) - 2011
- [j3]Borivoje Nikolic, Ji-Hoon Park, Jaehwa Kwak, Bastien Giraud, Zheng Guo, Liang-Teck Pang, Seng Oon Toh, Ruzica Jevtic, Kun Qian, Costas J. Spanos:
Technology Variability From a Design Perspective. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 1996-2009 (2011) - [j2]Ruzica Jevtic, Carlos Carreras:
Power Measurement Methodology for FPGA Devices. IEEE Trans. Instrum. Meas. 60(1): 237-247 (2011) - [c5]Ruzica Jevtic, Bojan Jovanovic, Carlos Carreras:
Power estimation of dividers implemented in FPGAs. ACM Great Lakes Symposium on VLSI 2011: 313-318 - 2010
- [j1]Ruzica Jevtic, Carlos Carreras:
Power Estimation of Embedded Multiplier Blocks in FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 18(5): 835-839 (2010)
2000 – 2009
- 2009
- [c4]Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic:
Floorplan-based FPGA interconnect power estimation in DSP circuits. SLIP 2009: 53-60 - 2008
- [c3]Ruzica Jevtic, Carlos Carreras:
Analytical High-Level Power Model for LUT-Based Components. PATMOS 2008: 369-378 - [c2]Ruzica Jevtic, Carlos Carreras, Domenik Helms:
A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. ReConFig 2008: 361-366 - 2007
- [c1]Ruzica Jevtic, Carlos Carreras, Gabriel Caffarena:
Switching Activity Models for Power Estimation in FPGA Multipliers. ARC 2007: 201-213
Coauthor Index
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