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Hsiang-Yun Cheng

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affiliation: Academia Sinica, Taiwan

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2020 – today

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2025
[c27]
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Tsung-Yu Liu, Yen-An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng:
ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. ASP-DAC 2025: 79-85
[c26]
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Hao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Andy Wu:
Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning. ASP-DAC 2025: 93-99
[c25]
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You-Kai Zheng, Ming-Liang Wei, Hsiang-Yun Cheng, Chia-Lin Yang, Ming-Hsiang Tsai, Chia-Chun Chien, Yuan-Hao Zhong, Po-Hao Tseng, Hsiang-Pang Li:
In-Storage Read-Centric Seed Location Filtering Using 3D-NAND Flash for Genome Sequence Analysis. ASP-DAC 2025: 1008-1015
2024
[c24]
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Chi-Tse Huang, Cheng-Yang Chang, Hsiang-Yun Cheng, An-Yeu Wu:
BORE: Energy-Efficient Banded Vector Similarity Search with Optimized Range Encoding for Memory-Augmented Neural Network. DATE 2024: 1-6
[c23]
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Tsung-Yu Liu, Yen-An Lu, James Yu, Chin-Fu Nien, Hsiang-Yun Cheng:
ReTAP: Processing-in-ReRAM Bitap Approximate String Matching Accelerator for Genomic Analysis. DATE 2024: 1-2
[c22]
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Hao-Wei Chiang, Chin-Fu Nien, Hsiang-Yun Cheng, Kuei-Po Huang:
ReAIM: A ReRAM-based Adaptive Ising Machine for Solving Combinatorial Optimization Problems. ISCA 2024: 58-72
[i2]
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  - journals/corr/abs-2409-07832
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Hao-Wei Chiang, Chi-Tse Huang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Wu:
Efficient and Reliable Vector Similarity Search Using Asymmetric Encoding with NAND-Flash for Many-Class Few-Shot Learning. CoRR abs/2409.07832 (2024)
2023
[c21]
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  - conf/cases/HenkelSBTWTMCKFLCHCYC23
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Jörg Henkel, Lokesh Siddhu, Lars Bauer, Jürgen Teich, Stefan Wildermann, Mehdi B. Tahoori, Mahta Mayahinia, Jerónimo Castrillón, Asif Ali Khan, Hamid Farzaneh, João Paulo C. de Lima, Jian-Jia Chen, Christian Hakert, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng:
Special Session - Non-Volatile Memories: Challenges and Opportunities for Embedded System Architectures with Focus on Machine Learning Applications. CASES 2023: 11-20
[c20]
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  - conf/hpca/LinCCY23
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Shao-Fu Lin, Yi-Jung Chen, Hsiang-Yun Cheng, Chia-Lin Yang:
Tensor Movement Orchestration in Multi-GPU Training Systems. HPCA 2023: 1140-1152
2022
[j5]
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  - journals/tecs/LinCYLLHCLCTN22
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Wei-Ting Lin, Hsiang-Yun Cheng, Chia-Lin Yang, Meng-Yao Lin, Kai Lien, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang, Yen-Ting Tsou, Chin-Fu Nien:
DL-RSIM: A Reliability and Deployment Strategy Simulation Framework for ReRAM-based CNN Accelerators. ACM Trans. Embed. Comput. Syst. 21(3): 24:1-24:29 (2022)
[c19]
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Yen-Ting Tsou, Kuan-Hsun Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Jian-Jia Chen, Der-Yu Tsai:
This is SPATEM! A Spatial-Temporal Optimization Framework for Efficient Inference on ReRAM-based CNN Accelerator. ASP-DAC 2022: 702-707
[c18]
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Ting Wu, Chin-Fu Nien, Kuang-Chao Chou, Hsiang-Yun Cheng:
RePAIR: A ReRAM-based Processing-in-Memory Accelerator for Indel Realignment. DATE 2022: 400-405
[c17]
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  - conf/hpca/YenHCCYCL22
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Jui-Nan Yen, Yao-Ching Hsieh, Cheng-Yu Chen, Tseng-Yi Chen, Chia-Lin Yang, Hsiang-Yun Cheng, Yixin Luo:
Efficient Bad Block Management with Cluster Similarity. HPCA 2022: 503-513
[c16]
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  - conf/iccel/ChouCQCCC22
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He-Sheng Chou, Hsiang-Yun Cheng, Jun-Xiang Qiu, Tsun-Kuang Chi, Tsung-Yi Chen, Shin-Lun Chen:
Retinex Based on Weaken Factor with Truncated AGCWD for Backlight Image Enhancement. ICCE 2022: 1-5
[c15]
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  - conf/nvmsa/DongCYLL22
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Nai-Jia Dong, Hsiang-Yun Cheng, Chia-Lin Yang, Bo-Rong Lin, Hsiang-Pang Li:
Efficient and Atomic-Durable Persistent Memory through In-PM Hybrid Logging. NVMSA 2022: 1-7
2021
[c14]
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  - conf/dac/TsaiNYYC21
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Chen-Yang Tsai, Chin-Fu Nien, Tz-Ching Yu, Hung-Yu Yeh, Hsiang-Yun Cheng:
RePIM: Joint Exploitation of Activation and Weight Repetitions for In-ReRAM DNN Acceleration. DAC 2021: 589-594
[c13]
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  - conf/date/ChengWHC0CYK21
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Hsiang-Yun Cheng, Chun-Feng Wu, Christian Hakert, Kuan-Hsun Chen, Yuan-Hao Chang, Jian-Jia Chen, Chia-Lin Yang, Tei-Wei Kuo:
Future Computing Platform Design: A Cross-Layer Design Approach. DATE 2021: 312-317
[c12]
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  - conf/iccd/HsiaoNC21
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Yi-Jou Hsiao, Chin-Fu Nien, Hsiang-Yun Cheng:
ReSpar: Reordering Algorithm for ReRAM-based Sparse Matrix-Vector Multiplication Accelerator. ICCD 2021: 260-268
[c11]
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  - conf/ispass/KeCYH21
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Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang, Han-Wei Huang:
Analyzing the Interplay Between Random Shuffling and Storage Devices for Efficient Machine Learning. ISPASS 2021: 276-287
2020
[c10]
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  - conf/date/NienHCWKL20
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Chin-Fu Nien, Yi-Jou Hsiao, Hsiang-Yun Cheng, Cheng-Yu Wen, Ya-Cheng Ko, Che-Ching Lin:
GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph Processing. DATE 2020: 1478-1483

2010 – 2019

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2019
[j4]
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  - journals/tc/LuoCLC19
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Jing-Yuan Luo, Hsiang-Yun Cheng, Ing-Chao Lin, Da-Wei Chang:
TAP: Reducing the Energy of Asymmetric Hybrid Last-Level Cache via Thrashing Aware Placement and Migration. IEEE Trans. Computers 68(12): 1704-1719 (2019)
[c9]
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Jörg Henkel, Hussam Amrouch, Martin Rapp, Sami Salamin, Dayane Reis, Di Gao, Xunzhao Yin, Michael T. Niemier, Cheng Zhuo, Xiaobo Sharon Hu, Hsiang-Yun Cheng, Chia-Lin Yang:
The Impact of Emerging Technologies on Architectures and System-level Management: Invited Paper. ICCAD 2019: 1-6
[c8]
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  - conf/isca/YangCYTHCL19
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Tzu-Hsien Yang, Hsiang-Yun Cheng, Chia-Lin Yang, I-Ching Tseng, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li:
Sparse ReRAM engine: joint exploration of activation and weight sparsity in compressed neural networks. ISCA 2019: 236-249
2018
[c7]
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  - conf/iccad/LinCLYTYHCLC18
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Meng-Yao Lin, Hsiang-Yun Cheng, Wei-Ting Lin, Tzu-Hsien Yang, I-Ching Tseng, Chia-Lin Yang, Han-Wen Hu, Hung-Sheng Chang, Hsiang-Pang Li, Meng-Fan Chang:
DL-RSIM: a simulation framework to enable reliable ReRAM-based accelerators for deep learning. ICCAD 2018: 31
[i1]
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  - journals/corr/abs-1810-04509
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Zhi-Lin Ke, Hsiang-Yun Cheng, Chia-Lin Yang:
LIRS: Enabling efficient machine learning on NVM-based storage via a lightweight implementation of random shuffling. CoRR abs/1810.04509 (2018)
2017
[j3]
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  - journals/cal/ChenCWY17
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Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang:
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. IEEE Comput. Archit. Lett. 16(2): 127-131 (2017)
[c6]
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  - conf/ispass/WangTWCWCLSYHKL17
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Li Wang, Ren-Wei Tsai, Shao-Chung Wang, Kun-Chih Chen, Po-Han Wang, Hsiang-Yun Cheng, Yi-Chung Lee, Sheng-Jie Shu, Chun-Chieh Yang, Min-Yih Hsu, Li-Chen Kan, Chao-Lin Lee, Tzu-Chieh Yu, Rih-Ding Peng, Chia-Lin Yang, Yuan-Shin Hwang, Jenq Kuen Lee, Shiao-Li Tsao, Ming Ouhyoung:
Analyzing OpenCL 2.0 workloads using a heterogeneous CPU-GPU simulator. ISPASS 2017: 127-128
2016
[c5]
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  - conf/isca/ChengZSIJL016
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Hsiang-Yun Cheng, Jishen Zhao, Jack Sampson, Mary Jane Irwin, Aamer Jaleel, Yu Lu, Yuan Xie:
LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches. ISCA 2016: 103-114
[c4]
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  - conf/iscas/ChangCCSKCSI16
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Meng-Fan Chang, Ching-Hao Chuang, Yen-Ning Chiang, Shyh-Shyuan Sheu, Chia-Chen Kuo, Hsiang-Yun Cheng, John Sampson, Mary Jane Irwin:
Designs of emerging memory based non-volatile TCAM for Internet-of-Things (IoT) and big-data processing: A 5T2R universal cell. ISCAS 2016: 1142-1145
2015
[j2]
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  - journals/taco/ChengPSSIKS015
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Hsiang-Yun Cheng, Matt Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie:
EECache: A Comprehensive Study on the Architectural Design for Energy-Efficient Last-Level Caches in Chip Multiprocessors. ACM Trans. Archit. Code Optim. 12(2): 17:1-17:22 (2015)
[j1]
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Hsiang-Yun Cheng, Mary Jane Irwin, Yuan Xie:
Adaptive Burst-Writes (ABW): Memory Requests Scheduling to Reduce Write-Induced Interference. ACM Trans. Design Autom. Electr. Syst. 21(1): 7:1-7:26 (2015)
[c3]
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  - conf/dac/ChengZZ0SI15
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Hsiang-Yun Cheng, Jia Zhan, Jishen Zhao, Yuan Xie, Jack Sampson, Mary Jane Irwin:
Core vs. uncore: the heart of darkness. DAC 2015: 121:1-121:6
2014
[c2]
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  - conf/islped/ChengPSSIKSX14
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Hsiang-Yun Cheng, Matthew Poremba, Narges Shahidi, Ivan Stalev, Mary Jane Irwin, Mahmut T. Kandemir, Jack Sampson, Yuan Xie:
EECache: exploiting design choices in energy-efficient last-level caches for chip multiprocessors. ISLPED 2014: 303-306
2010
[c1]
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  - conf/micro/ChengLLY10
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Hsiang-Yun Cheng, Chung-Hsiang Lin, Jian Li, Chia-Lin Yang:
Memory Latency Reduction via Thread Throttling. MICRO 2010: 53-64

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