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2020 – today
- 2021
[c5]Yong-Hun Kim, Hyung-Jin Kim, Jaemin Choi, Min-Su Ahn, Dongkeon Lee, Seung-Hyun Cho, Dong-Yeon Park, Young-Jae Park, Min-Soo Jang, Yong-Jun Kim, Jinyong Choi, Sung-Woo Yoon, Jae-Woo Jung, Jae-Koo Park, Jae-Woo Lee, Dae-Hyun Kwon, Hyung-Seok Cha, Si-Hyeong Cho, Seong-Hoon Kim, Jihwa You, Kyoung-Ho Kim, Dae-Hyun Kim, Byung-Cheol Kim, Young-Kwan Kim, Jun-Ho Kim, Seouk-Kyu Choi, Chanyoung Kim, Byongwook Na, Hye-In Choi, Reum Oh, Jeong-Don Ihm, Seung-Jun Bae, Nam Sung Kim, Jung-Bae Lee:
25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM. ISSCC 2021: 346-348
2010 – 2019
- 2019
- [j1]Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Min-Su Ahn, Yong-Hun Kim, Yong Jae Lee, Dong-Seok Kang, Sung-Geun Do, Chang-Yong Lee, Gun-hee Cho, Jae-Koo Park, Jae-Sung Kim, Kyung-Bae Park, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Hyun-Soo Park, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Yong-Jun Kim, Young-Hun Seo, Chang-Ho Shin, Chan-Yong Lee, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byung-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin:
A 16-Gb, 18-Gb/s/pin GDDR6 DRAM With Per-Bit Trainable Single-Ended DFE and PLL-Less Clocking. IEEE J. Solid State Circuits 54(1): 197-209 (2019) - 2018
- [c4]Young-Ju Kim, Hye-Jung Kwon, Su-Yeon Doo, Yoon-Joo Eom, Young-Sik Kim, Min-Su Ahn, Yong-Hun Kim, Sang-Hoon Jung, Sung-Geun Do, Chang-Yong Lee, Jae-Sung Kim, Dong-Seok Kang, Kyung-Bae Park, Jung-Bum Shin, Jong-Ho Lee, Seung-Hoon Oh, Sang-Yong Lee, Ji-Hak Yu, Ji-Suk Kwon, Ki-Hun Yu, Chul-Hee Jeon, Sang-Sun Kim, Min-Woo Won, Gun-hee Cho, Hyun-Soo Park, Hyung-Kyu Kim, Jeong-Woo Lee, Seung-Hyun Cho, Keon-Woo Park, Jae-Koo Park, Yong Jae Lee, Yong-Jun Kim, Young-Hun Seo, Beob-Rae Cho, Chang-Ho Shin, Chan-Yong Lee, YoungSeok Lee, Yoon-Gue Song, Sam-Young Bang, Youn-Sik Park, Seouk-Kyu Choi, Byeong-Cheol Kim, Gong-Heum Han, Seung-Jun Bae, Hyuk-Jun Kwon, Jung-Hwan Choi, Young-Soo Sohn, Kwang-Il Park, Seong-Jin Jang:
A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking. ISSCC 2018: 204-206 - [c3]Jin-Hyeok Baek, Chang-Kyo Lee, Kiho Kim, Daesik Moon, Gil-Hoon Cha, Jin-Seok Heo
, Min-Su Ahn, Dong-Ju Kim, Jae-Joon Song, Seokhong Kwon, Jongmin Kim, Kyung-Soo Kim, Jinoh Ahn, Jeong-Sik Nam, Byung-Cheol Kim, Jeong-Hyeon Cho, Jeonghoon Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Ilgweon Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang:
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. VLSI Circuits 2018: 147-148 - 2016
- [c2]Hye-Yoon Joo, Seung-Jun Bae, Young-Soo Sohn, Young-Sik Kim, Kyung-Soo Ha, Min-Su Ahn, Young-Ju Kim, Yong-Jun Kim, Ju-Hwan Kim, Won-Jun Choi, Chang-Ho Shin, Soo Hwan Kim, Byeong-Cheol Kim, Seung-Bum Ko, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin:
18.1 A 20nm 9Gb/s/pin 8Gb GDDR5 DRAM with an NBTI monitor, jitter reduction techniques and improved power distribution. ISSCC 2016: 314-315 - 2015
- [c1]Chang-Kyo Lee, Min-Su Ahn, Daesik Moon, Kiho Kim, Yoon-Joo Eom, Won-Young Lee, Jongmin Kim, Sanghyuk Yoon, Baekkyu Choi, Seokhong Kwon, Joon-Young Park, Seung-Jun Bae, Yong-Cheol Bae, Jung-Hwan Choi, Seong-Jin Jang, Gyo-Young Jin:
A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface. VLSIC 2015: 182-
Coauthor Index
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