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ORCIDCODES+ISSS 2012: Tampere, Finland
- Ahmed Jerraya, Luca P. Carloni, Naehyuck Chang, Franco Fummi:
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2012, part of ESWeek '12 Eighth Embedded Systems Week, Tampere, Finland, October 7-12, 2012. ACM 2012, ISBN 978-1-4503-1426-8
Keynotes
- Hannu Kauppinen:
Wireless innovations for smartphones. 1-2 - Satnam Singh:
Computing without processors. 3-4 - Jong-Deok Choi:
A standards-based, fully-open software platform for smart embedded systems. 5-6
ESWEEK special session
- Randolf Mock, Moritz Neukirchner, Rolf Ernst, Ruud Wijtvliet, Michael Huetwohl, Pascal Urard, Ovidiu Vermesan:
Internet-of-energy: combining embedded computing and communication for the smart grid. 7-8 - Dan Gunnarsson, Stefan Kuntz, Glenn Farrall, Akihito Iwai, Rolf Ernst:
Trends in automotive embedded systems. 9-10 - Petri Liuha, Kari Pehkonen, Juhani Rummukainen, Veli-Pekka Vatula, Tatu Koljonen:
Research issues in smart phones, notepads and related services. 11-12
Software solutions for handling physical effects in embedded platforms
- Adam S. Hartman, Donald E. Thomas:
Lifetime improvement through runtime wear-based task mapping. 13-22 - Shih-Hao Hung
, Chi-Sheng Shih, Tei-Wei Kuo, Chia-Heng Tu, Che-Wei Chang:
A real-time, energy-efficient system software suite for heterogeneous multicore platforms. 23-32 - Luis Angel D. Bathen, Mark Gottscho, Nikil D. Dutt, Alex Nicolau, Puneet Gupta:
ViPZonE: OS-level memory variability-driven physical address zoning for energy savings. 33-42
Robust embedded architecture
- Garo Bournoutian, Alex Orailoglu:
Dynamic transient fault detection and recovery for embedded processor datapaths. 43-52 - Mohammad Sajjad Hossain, Woo Suk Lee, Vijay Raghunathan:
SPI-SNOOPER: a hardware-software approach for transparent network monitoring in wireless sensor networks. 53-62 - Abbas BanaiyanMofrad, Gustavo Girão, Nikil D. Dutt:
A novel NoC-based design for fault-tolerance of last-level caches in CMPs. 63-72
Managing parallelism in multi-core systems
- Daniel Cordes, Michael Engel, Peter Marwedel, Olaf Neugebauer:
Automatic extraction of multi-objective aware pipeline parallelism using genetic algorithms. 73-82 - Mohamed Bamakhrama, Todor P. Stefanov:
Managing latency in embedded streaming applications under hard-real-time scheduling. 83-92 - Haeseung Lee, Weijia Che, Karam S. Chatha:
Dynamic scheduling of stream programs on embedded multi-core processors. 93-102
NOC and memory performance analysis and mapping
- Ciprian Seiculescu, Luca Benini, Giovanni De Micheli:
A distributed interleaving scheme for efficient access to WideIO DRAM memory. 103-112 - Nizar Dahir, Terrence S. T. Mak, Fei Xia, Alex Yakovlev:
Minimizing power supply noise through harmonic mappings in networks-on-chip. 113-122 - Gaoming Du, Cunqiang Zhang, Zhonghai Lu, Alberto Saggio, Minglun Gao:
Worst-case performance analysis of 2-D mesh NoCs using multi-path minimal routing. 123-132
Efficient simulation techniques
- Zhonglei Wang, Jörg Henkel:
HyCoS: hybrid compiled simulation of embedded software with target dependent code. 133-142 - Luc Michel, Nicolas Fournel, Frédéric Pétrot:
Fast simulation of systems embedding VLIW processors. 143-150 - Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran:
DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. 151-160
Routing algorithms and NoC architectures for next-generation 2D/3D SoCs
- Zhiliang Qian, Paul Bogdan, Guopeng Wei, Chi-Ying Tsui, Radu Marculescu:
A traffic-aware adaptive routing algorithm on a highly reconfigurable network-on-chip architecture. 161-170 - Miguel Salas, Sudeep Pasricha:
The roce-bush router: a case for routing-centric dimensional decomposition for low-latency 3D noC routers. 171-180 - Vladimir Todorov, Alberto Ghiribaldi, Helmut Reinig, Davide Bertozzi, Ulf Schlichtmann:
Non-intrusive trace & debug noc architecture with accurate timestamping for GALS SoCs. 181-186
Advanced simulation techniques for simulation-based validation
- Marco Bonato, Giuseppe Di Guglielmo, Masahiro Fujita, Franco Fummi, Graziano Pravadelli:
Dynamic property mining for embedded software. 187-196 - Ang Li, Mingsong Chen:
Efficient self-learning techniques for SAT-based test generation. 197-206 - Viraj Athavale, Sam Hertz, Darshan Jetly, Vijay Ganesan, Jim Krysl, Shobha Vasudevan:
Using static analysis for coverage extraction fromemulation/prototyping platforms. 207-214
Emulation of physical systems and design of wireless sensor networks
- Chen Huang, Bailey Miller, Frank Vahid, Tony Givargis:
Synthesis of custom networks of heterogeneous processing elements for complex physical system emulation. 215-224 - Paolo Roberto Grassi, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto:
Knowledge-based design space exploration of wireless sensor networks. 225-234 - Xuejing He, Robert P. Dick, Russ Joseph:
Spatially- and temporally-adaptive communication protocols for zero-maintenance sensor networks relying on opportunistic energy scavenging. 235-244
Advances in power/thermal optimization
- Emre Kultursay, Karthik Swaminathan, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta:
Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores. 245-254 - Thomas Ebi, Hussam Amrouch, Jörg Henkel:
COOL: control-based optimization of load-balancing for thermal behavior. 255-264 - Jingqing Mu, Roman L. Lysecky:
Adaptive online heuristic performance estimation and power optimization for reconfigurable embedded systems. 265-274
Enabling hardware design in system context
- James Coole, Greg Stitt:
BPR: fast FPGA placement and routing using macroblocks. 275-284 - Ralf Dreesen:
Generating interlocked instruction pipelines from specifications of instruction sets. 285-294 - Shahzad Ahmad Butt, Luciano Lavagno:
Designing parameterized signal processing ips for high level synthesis in a model based design environment. 295-304
Special session: testbenches for advanced TLM verification
- Wolfgang Müller, Wolfgang Ecker:
Testbenches for advanced TLM verification. 305-306 - Wolfgang Ecker, Volkan Esen, Michael Velten, Tudor Timisescu:
SystemC as completing pillar in industrial OVM based verification environments. 307-312 - Marcio Ferreira da Silva Oliveira, Christoph Kuznik, Hoang Minh Le, Daniel Große, Finn Haedicke, Wolfgang Müller, Rolf Drechsler, Wolfgang Ecker, Volkan Esen:
The system verification methodology for advanced TLM verification. 313-322 - Marcelo Sousa, Alper Sen:
Generation of TLM testbenches using mutation testing. 323-332 - Giuseppe Di Guglielmo, Graziano Pravadelli:
A testbench specification language for SystemC verification. 333-342 - Nicola Bombieri, Sara Vinco, Valeria Bertacco, Debapriya Chatterjee:
SystemC simulation on GP-GPUs: CUDA vs. OpenCL. 343-352
Power-efficient mobile computing
- Wonwoo Jung, Chulkoo Kang, Chanmin Yoon, Dongwon Kim, Hojung Cha:
DevScope: a nonintrusive and online power analysis tool for smartphone hardware components. 353-362 - Lide Zhang, Mark S. Gordon, Robert P. Dick, Zhuoqing Morley Mao, Peter A. Dinda, Lei Yang:
ADEL: an automatic detector of energy leaks for smartphone applications. 363-372 - Andrea Tilli, Andrea Bartolini, Matteo Cacciari, Luca Benini:
Don't burn your mobile!: safe computational re-sprinting via model predictive control. 373-382
System-level synthesis and optimization
- Martin Lukasiewycz, Samarjit Chakraborty:
Concurrent architecture and schedule optimization of time-triggered automotive systems. 383-392 - Peter van Stralen, Andy D. Pimentel:
A SAFE approach towards early design space exploration of fault-tolerant multimedia MPSoCs. 393-402 - Dongwook Lee, Hyungman Park, Andreas Gerstlauer:
Synthesis of optimized hardware transactors from abstract communication specifications. 403-412
New advances in microfluidic chips
- Daniel T. Grissom, Philip Brisk:
Fast online synthesis of generally programmable digital microfluidic biochips. 413-422 - Pranab Roy, Rupam Bhattacharjee, Modud Sohid, Sudipta Chakraborty, Hafizur Rahaman, Parthasarathi Dasgupta:
An intelligent compaction technique for pin constrained routing in cross referencing digital microfluidic biochips. 423-432
Power, reliability, and security issues from systems to circuits
- Carlo Brandolese, William Fornaciari, Luigi Rucco, Federico Terraneo:
Enabling ultra-low power operation in high-end wireless sensor networks nodes. 433-442 - Fabian Oboril, Farshad Firouzi, Saman Kiamehr, Mehdi Baradaran Tahoori:
Reducing NBTI-induced processor wearout by exploiting the timing slack of instructions. 443-452 - Kazuyuki Tanimura, Nikil D. Dutt:
LRCG: latch-based random clock-gating for preventing power analysis side-channel attacks. 453-462
Real-time and mixed critical systems
- Firew Siyoum, Marc Geilen, Orlando Moreira, Henk Corporaal:
Worst-case throughput analysis of real-time dynamic streaming applications. 463-472 - Domitian Tamas-Selicean, Paul Pop, Wilfried Steiner:
Synthesis of communication schedules for TTEthernet-based mixed-criticality systems. 473-482 - Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel:
A hierarchical control scheme for energy quota distribution in hybrid distributed video coding. 483-492
Memory management
- Ming-Chang Yang, Yuan-Hao Chang, Po-Chun Huang, Tei-Wei Kuo:
Working-set-based address mapping for ultra-large-scaled flash devices. 493-502
Co-design in the real world
- Edoardo Paone, Gianluca Palermo, Vittorio Zaccaria, Cristina Silvano, Diego Melpignano, Germain Haugou, Thierry Lepley:
An exploration methodology for a customizable OpenCL stereo-matching application targeted to an industrial multi-cluster architecture. 503-512 - Sungpack Hong, Tayo Oguntebi, Jared Casper, Nathan Grasso Bronson, Christos Kozyrakis, Kunle Olukotun:
A case of system-level hardware/software co-design and co-verification of a commodity multi-processor system with custom hardware. 513-520 - Erwin de Kock, Jos Verhaegh, Serge Amougou:
A configurable test infrastructure using a mixed-language and mixed-level IP integration IP-XACT flow. 521-528
Special session: synthesis of executable extra-functional system-level models for timing and power exploration
- Fernando Herrera, Hector Posadas, Pablo Peñil, Eugenio Villar, Francisco Ferrero, Raúl Valencia:
A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models. 529-538 - Carlo Brandolese, William Fornaciari:
Software energy optimization through fine-grained function-level voltage and frequency scaling. 539-546 - Daniel Lorenz, Kim Grüttner, Nicola Bombieri, Valerio Guarnieri, Sara Bocchio:
From RTL IP to functional system-level models with extra-functional properties. 547-556 - Chantal Ykman-Couvreur, Philipp A. Hartmann, Gianluca Palermo, Fabien Colas-Bigey, Laurent San:
Run-time resource management based on design space exploration. 557-566 - Parinaz Sayyah, Mihai T. Lazarescu, Davide Quaglia, Emad Samuel Malki Ebeid, Sara Bocchio, Alberto Rosti:
Network-aware design-space exploration of a power-efficient embedded application. 567-574
Tutorial
- Tom Vander Aa, Panagiotis Theocharis:
Hands-on tutorial: coarse-grained reconfigurable architectures - compilation and exploration. 575-576 - Kyoungwoo Lee, Aviral Shrivastava, Reiley Jeyapaul:
Soft errors: the hardware-software interface. 577-578
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