"Layout-driven test-architecture design and optimization for 3D SoCs under ..."

Li Jiang et al. (2009)

> Home

Details and statistics

DOI: 10.1145/1687399.1687434

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-21

- view
  authority control:
- export record
  dblp key:
  - conf/iccad/JiangXCM09
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/iccad/JiangXCM09
Li Jiang, Qiang Xu, Krishnendu Chakrabarty, T. M. Mak:
Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint. ICCAD 2009: 191-196

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.