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2010 – 2019
- 2016
[c9]Yi Diao, Xing Wei, Tak-Kei Lam, Yu-Liang Wu:
Coupling reverse engineering and SAT to tackle NP-complete arithmetic circuitry verification in ∼O(# of gates). ASP-DAC 2016: 139-146- 2015
- [c8]Yi Diao, Tak-Kei Lam, Xing Wei, Yu-Liang Wu:
A coupling area reduction technique applying ODC shifting. DATE 2015: 1461-1466 - [c7]Xing Wei, Yi Diao, Tak-Kei Lam, Yu-Liang Wu:
A universal macro block mapping scheme for arithmetic circuits. DATE 2015: 1629-1634 - 2014
- [c6]Tak-Kei Lam, Xing Wei, Wen-Ben Jone, Yi Diao, Yu-Liang Wu:
On macro-fault: a new fault model, its implications on fault tolerance and manufacturing yield. ACM Great Lakes Symposium on VLSI 2014: 233-234 - [c5]Xing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu:
Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted Wire. VLSID 2014: 375-380 - 2012
- [j2]Tak-Kei Lam, Wai-Chung Tang, Xiaoqing Yang, Yu-Liang Wu:
ECR: A Powerful and Low-Complexity Error Cancellation Rewiring Scheme. ACM Trans. Design Autom. Electr. Syst. 17(4): 50:1-50:21 (2012) - [c4]Xiaoqing Yang, Tak-Kei Lam, Wai-Chung Tang, Yu-Liang Wu:
Almost every wire is removable: A modeling and solution for removing any circuit wire. DATE 2012: 1573-1578 - 2011
- [j1]Fu-Shing Chim, Tak-Kei Lam, Yu-Liang Wu, Hongbing Fan:
On Structural Analysis and Efficiency for Graph-Based Rewiring Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 94-A(12): 2853-2865 (2011) - [c3]Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yu-Liang Wu:
On applying erroneous clock gating conditions to further cut down power. ASP-DAC 2011: 509-514 - 2010
- [c2]Xiaoqing Yang, Tak-Kei Lam, Yu-Liang Wu:
ECR: a low complexity generalized error cancellation rewiring scheme. DAC 2010: 511-516 - [c1]Tak-Kei Lam, Steve Yang, Wai-Chung Tang, Yu-Liang Wu:
Logic synthesis for low power using clock gating and rewiring. ACM Great Lakes Symposium on VLSI 2010: 179-184
Coauthor Index
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