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ORCIDSharareh Zamanzadeh
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2010 – 2019
- 2017
[c5]Sharareh Zamanzadeh, Ali Jahanian:
Scalable security path methodology: A cost-security trade-off to protect FPGA IPs against active and passive tampers. AsianHOST 2017: 85-90- 2016
- [j5]Sharareh Zamanzadeh, Ali Jahanian
:
Security Path: An Emerging Design Methodology to Protect the FPGA IPs Against Passive/Active Design Tampering. J. Electron. Test. 32(3): 329-343 (2016) - [j4]Sharareh Zamanzadeh, Ali Jahanian:
Self authentication path insertion in FPGA-based design flow for tamper-resistant purpose. ISC Int. J. Inf. Secur. 8(1): 53-60 (2016) - [j3]Sharareh Zamanzadeh, Ali Jahanian:
ASIC design protection against reverse engineering during the fabrication process using automatic netlist obfuscation design flow. ISC Int. J. Inf. Secur. 8(2): 93-104 (2016) - [j2]Sharareh Zamanzadeh, Ali Jahanian:
Higher security of ASIC fabrication process against reverse engineering attack using automatic netlist encryption methodology. Microprocess. Microsystems 42: 1-9 (2016) - [c4]Sharareh Zamanzadeh, Shahram Shahabi, Ali Jahanian:
Security improvement of FPGA configuration file against the reverse engineering attack. ISCISC 2016: 101-105 - 2013
- [j1]Shima Mehrabi, Reza Faghih Mirzaee, Sharareh Zamanzadeh, Keivan Navi, Omid Hashemipour:
Design, analysis, and implementation of partial product reduction phase by using wide m: 3 (4 ≤ m ≤ 10) compressors. Int. J. High Perform. Syst. Archit. 4(4): 231-241 (2013) - [c3]Sharareh Zamanzadeh, Ali Jahanian:
Automatic netlist scrambling methodology in ASIC design flow to hinder the reverse engineering. VLSI-SoC 2013: 52-53
2000 – 2009
- 2008
- [c2]Sharareh Zamanzadeh, Mehrdad Najibi, Hossein Pedram:
Pre-synthesis Optimization for Asynchronous Circuits Using Compiler Techniques. CSICC 2008: 951-954 - [c1]Sharareh Zamanzadeh, Mohammad Mirza-Aghatabar, Mehrdad Najibi, Hossein Pedram, Abolghasem Sadeghi:
Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations. DSD 2008: 290-297
Coauthor Index
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