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ORCIDGopalakrishnan Vijayan
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1990 – 1999
- 1997
[c11]Sergey Gavrilov, Alexey Glebov, Sergey G. Rusakov
, David T. Blaauw, Larry G. Jones, Gopalakrishnan Vijayan:
Fast power loss calculation for digital static CMOS circuits. ED&TC 1997: 411-415- [c10]Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw:
Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662 - 1995
- [c9]Vinod Narayananan, David LaPotin, Rajesh Gupta, Gopalakrishnan Vijayan:
PEPPER - a timing driven early floorplanner. ICCD 1995: 230-235 - 1992
- [j15]Vijay S. Iyengar, Gopalakrishnan Vijayan:
Optimized test application timing for AC test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(11): 1439-1449 (1992) - [c8]Pradip Bose, David LaPotin, Gopalakrishnan Vijayan, Sungho Kim:
Workload-Driven Floorplanning for MIPS Optimization. ICCD 1992: 387-391 - 1991
- [j14]Ananth V. Iyer, H. Donald Ratliff, Gopalakrishnan Vijayan:
On an edge ranking problem of trees and graphs. Discret. Appl. Math. 30(1): 43-52 (1991) - [j13]Jan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong:
Planar topological routing of pad nets. Integr. 11(3): 295-316 (1991) - [j12]Gopalakrishnan Vijayan:
Generalization of Min-Cut Partitioning to Tree Structures and Its Applications. IEEE Trans. Computers 40(3): 307-314 (1991) - [j11]Gopalakrishnan Vijayan, Ren-Song Tsay:
A new method for floor planning using topological constraint reduction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(12): 1494-1501 (1991) - [c7]Vijay S. Iyengar, Gopalakrishnan Vijayan:
Test Application Timing: The Unexplored Issue in AC Test. ITC 1991: 840-847 - 1990
- [j10]Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong:
New algorithms for the rectilinear Steiner tree problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(2): 185-193 (1990) - [j9]Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong:
Pad minimization for planar routing of multiple power nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(4): 419-426 (1990) - [j8]Jan-Ming Ho, Majid Sarrafzadeh, Gopalakrishnan Vijayan, Chak-Kuen Wong:
Layer assignment for multichip modules. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1272-1277 (1990) - [j7]Gopalakrishnan Vijayan:
Partitioning logic on graph structures to minimize routing cost. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(12): 1326-1334 (1990) - [c6]Gopalakrishnan Vijayan, Ren-Song Tsay:
Floorplanning by Topological Constraint Reduction. ICCAD 1990: 106-109
1980 – 1989
- 1989
- [j6]Gopalakrishnan Vijayan, Hai Hsia Chen, Chak-Kuen Wong:
On VHV-routing in channels with irregular boundaries. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(2): 146-152 (1989) - [c5]Jan-Ming Ho, Gopalakrishnan Vijayan, C. K. Wong:
A New Approach to the Rectilinear Steiner Tree Problem. DAC 1989: 161-166 - [c4]Gopalakrishnan Vijayan:
Min-cost Partitioning on a Tree Structure and Applications. DAC 1989: 771-774 - [c3]Jan-Ming Ho, Gopalakrishnan Vijayan, Chak-Kuen Wong:
Constructing the optimal rectilinear Steiner tree derivable from a minimum spanning tree. ICCAD 1989: 6-9 - 1988
- [j5]Ananth V. Iyer, H. Donald Ratliff, Gopalakrishnan Vijayan:
Optimal Node Ranking of Trees. Inf. Process. Lett. 28(5): 225-229 (1988) - 1987
- [j4]Jeremy P. Spinrad, Gopalakrishnan Vijayan, Douglas B. West:
An improved edge bound on the interval number of a graph. J. Graph Theory 11(3): 447-449 (1987) - 1986
- [c2]Gopalakrishnan Vijayan:
Geometry of Planar Graphs with Angles. SCG 1986: 116-124 - 1985
- [j3]Jeremy P. Spinrad, Gopalakrishnan Vijayan:
Worst case analysis of a graph coloring algorithm. Discret. Appl. Math. 12(1): 89-92 (1985) - [j2]Gopalakrishnan Vijayan, Avi Wigderson:
Rectilinear Graphs and their Embeddings. SIAM J. Comput. 14(2): 355-372 (1985) - 1983
- [j1]Richard J. Lipton, Jacobo Valdes, Gopalakrishnan Vijayan, Stephen C. North, Robert Sedgewick:
VLSI Layout as Programming. ACM Trans. Program. Lang. Syst. 5(3): 405-421 (1983) - 1982
- [c1]Richard J. Lipton, Stephen C. North, Robert Sedgewick, Jacobo Valdes, Gopalakrishnan Vijayan:
ALI: A procedural language to describe VLSI layouts. DAC 1982: 467-474
Coauthor Index
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