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ORCIDSubramanian Rajagopalan
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2010 – 2019
- 2015
[c12]Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids. VLSID 2015: 186-191- 2014
- [c11]Sambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala:
Fixing Double Patterning violations with look-ahead. ASP-DAC 2014: 149-154 - 2013
- [c10]Nitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
Automatic design rule correction in presence of multiple grids and track patterns. DAC 2013: 26:1-26:6
2000 – 2009
- 2009
- [c9]Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala:
Efficient Analog/RF Layout Closure with Compaction Based Legalization. VLSI Design 2009: 137-142 - 2008
- [c8]Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy:
On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED 2008: 379-384 - [c7]Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy:
Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED 2008: 450-455 - 2007
- [c6]Subramanian Rajagopalan, Shabbir H. Batterywala:
A 3-dimensional FEM Based Resistance Extraction. VLSI Design 2007: 565-570 - [c5]Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou:
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880 - [p2]Subramanian Rajagopalan, Sharad Malik:
A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal Processors. The Compiler Design Handbook, 2nd ed. 2007: 18 - 2004
- [c4]Wei Qin, Subramanian Rajagopalan, Sharad Malik
:
A formal concurrency model based architecture description language for synthesis of software development tools. LCTES 2004: 47-56 - 2002
- [c3]Wei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh:
Design Tools for Application Specific Embedded Processors. EMSOFT 2002: 319-333 - [p1]Subramanian Rajagopalan, Sharad Malik:
Retargetable Very Long Instuction Word Compiler Framework for Digital Signal Processors. The Compiler Design Handbook 2002: 603-630 - 2001
- [j1]Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama:
A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(11): 1319-1328 (2001) - [c2]Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik:
Optimal Live Range Merge for Address Register Allocation in Embedded Programs. CC 2001: 274-288 - 2000
- [c1]Subramanian Rajagopalan, Manish Vachharajani, Sharad Malik:
Handling irregular ILP within conventional VLIW schedulers using artificial resource constraints. CASES 2000: 157-164
Coauthor Index
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