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2010 – 2019
- 2017
[c17]Harijot Singh Bindra, Joeri Lechevallier, Anne-Johan Annema, Simon M. Louwsma, Ed van Tuijl, Bram Nauta
:
Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. A-SSCC 2017: 217-220- [c16]Harijot Singh Bindra, Anne-Johan Annema, Simon M. Louwsma, Ed J. M. van Tuijl, Bram Nauta:
An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. ESSCIRC 2017: 235-238 - 2015
- [c15]Hugo Westerveld, Daniël Schinkel, Ed van Tuijl:
15.3 A 115dB-DR audio DAC with -61dBFS out-of-band noise. ISSCC 2015: 1-3 - [c14]Xicheng Jiang, Ed van Tuijl:
Session 5 overview: Analog techniques: Analog subcommittee. ISSCC 2015: 86-87 - 2014
- [j11]Paul F. J. Geraedts, Ed J. M. van Tuijl, Eric A. M. Klumperink, Gerard J. M. Wienk, Bram Nauta:
Towards minimum achievable phase noise of relaxation oscillators. Int. J. Circuit Theory Appl. 42(3): 238-257 (2014) - 2011
- [c13]Fabian van Houwelingen, Ed van Tuijl, Bram Nauta, Maarten Vertregt:
A narrow-to-wideband scrambling technique increasing software radio receiver linearity. ESSCIRC 2011: 535-538 - 2010
- [j10]Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects. IEEE J. Solid State Circuits 45(2): 447-457 (2010) - [j9]Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta:
A 10-bit Charge-Redistribution ADC Consuming 1.9 μ W at 1 MS/s. IEEE J. Solid State Circuits 45(5): 1007-1015 (2010)
2000 – 2009
- 2009
- [j8]Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
Low-Power, High-Speed Transceivers for Network-on-Chip Communication. IEEE Trans. Very Large Scale Integr. Syst. 17(1): 12-21 (2009) - 2008
- [j7]Simon M. Louwsma, A. J. M. van Tuijl, Maarten Vertregt, Bram Nauta:
A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. IEEE J. Solid State Circuits 43(4): 778-786 (2008) - [c12]Ed van Tuijl, Ken Chang:
Session 20 - Advanced wireline techniques. CICC 2008 - [c11]Marco Berkhout, Lucien J. Breems, Ed van Tuijl:
Audio at low and high power. ESSCIRC 2008: 40-49 - [c10]Michiel van Elzakker, Ed van Tuijl, Paul F. J. Geraedts, Daniël Schinkel, Eric A. M. Klumperink, Bram Nauta:
A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC. ISSCC 2008: 244-245 - [c9]Paul F. J. Geraedts, Ed van Tuijl, Eric A. M. Klumperink, Gerard Wienk, Bram Nauta:
A 90μW 12MHz Relaxation Oscillator with a -162dB FOM. ISSCC 2008: 348-349 - 2007
- [j6]Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
Optimal Positions of Twists in Global On-Chip Differential Interconnects. IEEE Trans. Very Large Scale Integr. Syst. 15(4): 438-446 (2007) - [c8]Simon M. Louwsma, Ed van Tuijl, Maarten Vertregt, Bram Nauta:
A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. CICC 2007: 329-332 - [c7]Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time. ISSCC 2007: 314-605 - [c6]Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects. ISSCC 2007: 414-612 - 2006
- [j5]Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed J. M. van Tuijl, Bram Nauta:
A 3-Gb/s/ch transceiver for 10-mm uninterrupted RC-limited global on-chip interconnects. IEEE J. Solid State Circuits 41(1): 297-306 (2006) - 2005
- [c5]T. S. Doorn, Ed van Tuijl, Daniël Schinkel, Anne-Johan Annema, Marco Berkhout, Bram Nauta:
An audio FIR-DAC in a BCD process for high power class-D amplifiers. ESSCIRC 2005: 459-462 - [c4]Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
Optimally-placed twists in global on-chip differential interconnects. ESSCIRC 2005: 475-478 - 2004
- [c3]Simon M. Louwsma, Ed J. M. van Tuijl, Maarten Vertregt, Peter C. S. Scholtens, Bram Nauta:
A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. ESSCIRC 2004: 343-346 - [c2]Daniël Schinkel, Ed van Tuijl, Anne-Johan Annema:
Reducing quantization noise with recursive Sigma Delta modulators. ISCAS (1) 2004: 1084-1087 - 2002
- [j4]Sander L. J. Gierkink, Ed van Tuijl:
A coupled sawtooth oscillator combining low jitter with high control linearity. IEEE J. Solid State Circuits 37(6): 702-710 (2002)
1990 – 1999
- 1999
- [j3]Ronan A. R. van der Zee, Ed A. J. M. van Tuijl:
A power-efficient audio amplifier combining switching and linear techniques. IEEE J. Solid State Circuits 34(7): 985-991 (1999) - [j2]Sander L. J. Gierkink, Eric A. M. Klumperink, Arnoud P. van der Wel, Gian Hoogzaad, Ed A. J. M. van Tuijl, Bram Nauta:
Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators. IEEE J. Solid State Circuits 34(7): 1022-1025 (1999) - 1998
- [c1]Mihai A. T. Sanduleanu, A. J. M. van Tuijl, R. F. Wassenaar, M. C. Lammers, H. Wallinga:
A low noise, low residual offset, chopped amplifier for mixed level applications. ICECS 1998: 333-336 - 1996
- [j1]Eric A. M. Klumperink, Carlo T. Klein, Bas Rüggeberg, Ed J. M. van Tuijl:
AM suppression with low AM-PM conversion with the aid of a variable-gain amplifier. IEEE J. Solid State Circuits 31(5): 625-633 (1996)
Coauthor Index
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