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ORCIDFatemeh Refan
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2010 – 2019
- 2018
[j2]Fatemeh Refan, Bijan Alizadeh
, Zainalabedin Navabi:
Scalable Symbolic Simulation-Based Automatic Correction of Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 1845-1853 (2018)- 2017
- [j1]Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi:
Bridging Presilicon and Postsilicon Debugging by Instruction-Based Trace Signal Selection in Modern Processors. IEEE Trans. Very Large Scale Integr. Syst. 25(7): 2059-2070 (2017) - 2015
- [c8]Fatemeh Refan, Bijan Alizadeh, Zainalabedin Navabi:
Signature oriented model pruning to facilitate multi-threaded processors debugging. VTS 2015: 1-6 - 2011
- [c7]Hoda Ahmadinejad, Fatemeh Refan, Hessam S. Sarjoughian:
NoC simulation modeling in DEVS-suite. SpringSim (TMS-DEVS) 2011: 134-139
2000 – 2009
- 2009
- [c6]Alireza Aminlou, Fatemeh Refan, Mahmoud Reza Hashemi, Omid Fatemi, Saeed Safari:
A cost-error optimized architecture for 9/7 lifting based Discrete Wavelet Transform with balanced pipeline stages. ICASSP 2009: 589-592 - 2008
- [c5]Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi:
An IEEE 1500 compatible wrapper architecture for testing cores at transaction level. EWDTS 2008: 178-181 - [c4]Fatemeh Refan, Homa Alemzadeh, Saeed Safari, Paolo Prinetto, Zainalabedin Navabi:
Reliability in Application Specific Mesh-Based NoC Architectures. IOLTS 2008: 207-212 - [c3]Homa Alemzadeh, Stefano Di Carlo, Fatemeh Refan, Paolo Prinetto, Zainalabedin Navabi:
"Plug & Test" at System Level via Testable TLM Primitives. ITC 2008: 1-10 - 2007
- [c2]Alireza Aminlou, Fatemeh Refan, Maryam Homayouni, Omid Fatemi, Mahmoud Reza Hashemi:
A Split Method for Optimized Cost-Quality Hardware Implementation of Lifting-Based Discrete Wavelet Transform. ICASSP (2) 2007: 89-92 - [c1]Alireza Aminlou, Fatemeh Refan, Mahmoud Reza Hashemi, Omid Fatemi:
Two Level Cost-Quality Optimization of 9-7 Lifting-Based Discrete Wavelet Transform. ICIP (6) 2007: 217-220
Coauthor Index
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