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ORCIDAlexey Kupriyanov
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2000 – 2009
- 2009
[b1]Alexey Kupriyanov:
Modeling and Efficient Simulation of Complex System-on-a-Chip Architectures (Modellierung und effiziente Simulation von komplexen System-on-a-Chip Architekturen). University of Erlangen-Nuremberg, Germany, 2009- [j1]Hritam Dutta, Dmitrij Kissler, Frank Hannig
, Alexey Kupriyanov, Jürgen Teich, Bernard Pottier:
A holistic approach for tightly coupled reconfigurable parallel processors. Microprocess. Microsystems 33(1): 53-62 (2009) - 2007
- [c10]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Julien Lallet, Olivier Sentieys, Sébastien Pillement:
Modeling of Interconnection Networks in Massively Parallel Processor Architectures. ARCS 2007: 268-282 - [c9]Hritam Dutta, Frank Hannig, Alexey Kupriyanov, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Bernard Pottier:
Massively Parallel Processor Architectures: A Co-design Approach. ReCoSoC 2007: 61-68 - [c8]Alexey Kupriyanov, Dmitrij Kissler, Frank Hannig, Jürgen Teich:
Efficient event-driven simulation of parallel processor architectures. SCOPES 2007: 71-80 - 2006
- [c7]Dmitrij Kissler, Alexey Kupriyanov, Frank Hannig, Dirk Koch, Jürgen Teich:
A Generic Framework for Rapid Prototyping of System-on-Chip Designs. CDES 2006: 189-195 - [c6]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
A highly parameterizable parallel processor array architecture. FPT 2006: 105-112 - [c5]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
Hardware Cost Analysis for Weakly Programmable Processor Arrays. SoC 2006: 1-4 - [c4]Alexey Kupriyanov, Frank Hannig, Dmitrij Kissler, Jürgen Teich, Rainer Schaffer, Renate Merker:
An Architecture Description Language for Massively Parallel Processor Architectures. MBMV 2006: 11-20 - [c3]Dmitrij Kissler, Frank Hannig, Alexey Kupriyanov, Jürgen Teich:
A Dynamically Reconfigurable Weakly Programmable Processor Array Architecture Template. ReCoSoC 2006: 31-37 - 2005
- [c2]Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Ménard, Olivier Sentieys:
Co-Design of Massively Parallel Embedded Processor Architectures. ReCoSoC 2005: 27-34 - 2004
- [c1]Alexey Kupriyanov, Frank Hannig, Jürgen Teich:
High-Speed Event-Driven RTL Compiled Simulation. SAMOS 2004: 519-529
Coauthor Index
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