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2010 – 2019
- 2018
[c3]Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham
:
A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications. COOL CHIPS 2018: 1-3
1990 – 1999
- 1995
- [j2]Atsushi Hasegawa, Ikuya Kawasaki, Kouji Yamada, Shinichi Yoshioka, Shumpei Kawasaki, Prasenjit Biswas:
SH3: high code density, low power. IEEE Micro 15(6): 11-19 (1995)
1980 – 1989
- 1989
- [j1]Shumpei Kawasaki, Mitsuru Watabe, Shigeki Morinaga:
A floating-point VLSI chip for the TRON architecture: an architecture for reliable numerical programming. IEEE Micro 9(3): 26-44 (1989) - 1986
- [c2]Shumpei Kawasaki, Tohru Nojiri, Kousuke Sakoda:
A User-Adaptable VLSI Engine for Artificial Intelligence. IFIP Congress 1986: 367-372 - [c1]Tohru Nojiri, Shumpei Kawasaki, Kousuke Sakoda:
Microprogrammable Processor for Object-Oriented Architecture. ISCA 1986: 74-81
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