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ORCIDPedro J. Gil
Pedro J. Gil-Vicente
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2020 – today
- 2024
[j16]Daniel Gil-Tomas
, Luis J. Saiz-Adalid, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Pedro J. Gil-Vicente:
A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays. IEEE Access 12: 70662-70675 (2024)
2010 – 2019
- 2019
- [j15]Luis J. Saiz-Adalid, Joaquin Gracia-Moran, Daniel Gil-Tomas, Juan-Carlos Baraza-Calvo, Pedro J. Gil-Vicente:
Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection. IEEE Access 7: 151131-151143 (2019) - 2018
- [j14]Joaquin Gracia-Moran, Luis J. Saiz-Adalid, Daniel Gil-Tomas, Pedro J. Gil-Vicente:
Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications. IEEE Trans. Very Large Scale Integr. Syst. 26(10): 2132-2142 (2018) - [c56]Joaquin Gracia-Moran, Luis J. Saiz-Adalid, Juan-Carlos Baraza-Calvo, Pedro J. Gil:
Correction of Adjacent Errors with Low Redundant Matrix Error Correction Codes. LADC 2018: 107-114 - 2016
- [j13]Daniel Gil-Tomas, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente:
Injecting Intermittent Faults for the Dependability Assessment of a Fault-Tolerant Microcomputer System. IEEE Trans. Reliab. 65(2): 648-661 (2016) - [c55]Luis J. Saiz-Adalid, Pedro J. Gil, Juan Carlos Ruiz, Joaquin Gracia-Moran, Daniel Gil-Tomas, Juan-Carlos Baraza-Calvo:
Ultrafast Error Correction Codes for Double Error Detection/Correction. EDCC 2016: 108-119 - [c54]Ilya Tuzov, Juan Carlos Ruiz, David de Andrés, Pedro J. Gil:
Speeding-Up Simulation-Based Fault Injection of Complex HDL Models. LADC 2016: 51-60 - 2015
- [j12]Luis J. Saiz-Adalid, Pedro Reviriego, Pedro J. Gil, Salvatore Pontarelli, Juan Antonio Maestro:
MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction. IEEE Trans. Very Large Scale Integr. Syst. 23(10): 2332-2336 (2015) - [c53]Luis J. Saiz-Adalid, Pedro J. Gil, Joaquin Gracia-Moran, Daniel Gil-Tomas, Juan-Carlos Baraza-Calvo:
Ultrafast Single Error Correction Codes for Protecting Processor Registers. EDCC 2015: 144-154 - [c52]Jaime Espinosa, David de Andrés, Pedro J. Gil:
Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults. EDCC 2015: 190-197 - 2014
- [j11]Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Daniel Gil-Tomas, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente:
Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor. IEEE Trans. Reliab. 63(1): 144-153 (2014) - [c51]Luis J. Saiz-Adalid, Pedro J. Gil, Juan-Carlos Baraza-Calvo, Juan-Carlos Ruiz-Garcia, Daniel Gil-Tomas, Joaquin Gracia-Moran:
Modified Hamming Codes to Enhance Short Burst Error Detection in Semiconductor Memories (Short Paper). EDCC 2014: 62-65 - 2013
- [c50]Jaime Espinosa, David de Andrés, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs. EWDC 2013: 76-87 - [c49]Joaquin Gracia-Moran, Juan-Carlos Ruiz-Garcia, Juan-Carlos Baraza-Calvo, David de Andrés, Pedro J. Gil:
Improving the Transfer of Safety and Security Competences to Industry: The RISKY Approach. EWDC 2013: 185-189 - [c48]Luis J. Saiz-Adalid, Pedro J. Gil, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo:
Using Interleaving to Avoid the Effects of Multiple Adjacent Faults in On-Chip Interconnection Lines. EWDC 2013: 198-201 - [c47]Joaquin Gracia-Moran, Daniel Gil-Tomas, Luis J. Saiz-Adalid, Juan-Carlos Baraza-Calvo, Pedro J. Gil-Vicente:
Defining a Representative and Low Cost Fault Model Set for Intermittent Faults in Microprocessor Buses. LADC 2013: 98-103 - [c46]Luis J. Saiz-Adalid, Pedro J. Gil-Vicente, Juan-Carlos Ruiz-Garcia, Daniel Gil-Tomas, Juan Carlos Baraza, Joaquin Gracia-Moran:
Flexible Unequal Error Control Codes with Selectable Error Detection and Correction Levels. SAFECOMP 2013: 178-189 - 2012
- [j10]Daniel Gil-Tomas, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente:
Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection. IEEE Des. Test 29(6): 66-73 (2012) - [j9]Daniel Gil-Tomas, Joaquin Gracia-Moran, Juan-Carlos Baraza-Calvo, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente:
Studying the effects of intermittent faults on a microcontroller. Microelectron. Reliab. 52(11): 2837-2846 (2012) - [c45]Jaime Espinosa, David de Andrés, Juan Carlos Ruiz, Pedro J. Gil:
Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments. FPL 2012: 292-299 - 2011
- [j8]Jesus Friginal, David de Andrés, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
Towards benchmarking routing protocols in wireless mesh networks. Ad Hoc Networks 9(8): 1374-1388 (2011) - [c44]Jesus Friginal, David de Andrés, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
Coarse-grained resilience benchmarking using logic score of preferences: ad hoc networks as a case study. EWDC 2011: 23-28 - [c43]Jesus Friginal, David de Andrés, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
On Selecting Representative Faultloads to Guide the Evaluation of Ad Hoc Networks. LADC 2011: 94-99 - [c42]Jesus Friginal, David de Andrés, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
Using Performance, Energy Consumption, and Resilience Experimental Measures to Evaluate Routing Protocols for Ad Hoc Networks. NCA 2011: 139-146 - [c41]Jesus Friginal, David de Andrés, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
Resilience-Driven Parameterisation of Ad Hoc Routing Protocols: olsrd as a Case Study. SRDS 2011: 85-90 - 2010
- [c40]Joaquin Gracia-Moran, Daniel Gil-Tomas, Luis J. Saiz-Adalid, Juan Carlos Baraza, Pedro J. Gil-Vicente:
Experimental validation of a fault tolerant microcomputer system against intermittent faults. DSN 2010: 413-418 - [c39]Joaquin Gracia-Moran, Daniel Gil-Tomas, Juan Carlos Baraza, Luis J. Saiz-Adalid, Pedro J. Gil-Vicente:
Searching Representative and Low Cost Fault Models for Intermittent Faults in Microcontrollers: A Case Study. PRDC 2010: 11-18 - [c38]Jesus Friginal, David de Andrés, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
Attack Injection to Support the Evaluation of Ad Hoc Networks. SRDS 2010: 21-29
2000 – 2009
- 2009
- [j7]Sara Blanc, Alberto Bonastre, Pedro J. Gil:
Dependability assessment of by-wire control systems using fault injection. J. Syst. Archit. 55(2): 102-113 (2009) - [c37]Juan-Carlos Ruiz-Garcia, David de Andrés, Pedro J. Gil:
Design and Deployment of a Generic ECC-based Fault Tolerance Mechanism for Embedded HW Cores. ETFA 2009: 1-8 - [c36]David de Andrés, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
Using Dependability, Performance, Area and Energy Consumption Experimental Measures to Benchmark IP Cores. LADC 2009: 49-56 - [c35]David de Andrés, Jesus Friginal, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
An Attack Injection Approach to Evaluate the Robustness of Ad Hoc Networks. PRDC 2009: 228-233 - 2008
- [j6]David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil:
Fault Emulation for Dependability Evaluation of VLSI Systems. IEEE Trans. Very Large Scale Integr. Syst. 16(4): 422-431 (2008) - [j5]Juan Carlos Baraza, Joaquin Gracia, Sara Blanc, Daniel Gil, Pedro J. Gil:
Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code. IEEE Trans. Very Large Scale Integr. Syst. 16(6): 693-706 (2008) - [c34]Joaquin Gracia, Luis J. Saiz, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil:
Analysis of the influence of intermittent faults in a microcontroller. DDECS 2008: 80-85 - [c33]David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil:
Dependability Assessment for the Selection of Embedded Cores. EDCC 2008: 79-84 - [c32]Daniel Gil, Luis J. Saiz, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil:
Injecting intermittent faults for the dependability validation of commercial microcontrollers. HLDVT 2008: 177-184 - [c31]Juan-Carlos Ruiz-Garcia, David de Andrés, Sara Blanc, Pedro J. Gil:
Generic Design and Automatic Deployment of NMR Strategies on HW Cores. PRDC 2008: 265-272 - 2006
- [c30]David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil:
Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems. DSN 2006: 291-300 - [c29]Juan Pardo, José Carlos Campelo, Juan-Carlos Ruiz-Garcia, Pedro J. Gil:
Temporal Characterization of Embedded Systems Using Nexus. EDCC 2006: 47-52 - [c28]David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil:
Fast Emulation of Permanent Faults in VLSI Systems. FPL 2006: 1-6 - [c27]David de Andrés, Juan-Carlos Ruiz-Garcia, Daniel Gil, Pedro J. Gil:
FADES: a fault emulation tool for fast dependability assessment. FPT 2006: 221-228 - 2005
- [c26]David de Andrés, José Albaladejo, Lenin Lemus, Pedro J. Gil:
Fast Run-Time Reconfiguration for SEU Injection. EDCC 2005: 230-245 - [c25]Daniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil:
Impact of Faults in Combinational Logic of Commercial Microcontrollers. EDCC 2005: 379-390 - [c24]Juan Carlos Baraza, Joaquin Gracia, Daniel Gil, Pedro J. Gil:
Improvement of fault injection techniques based on VHDL code modification. HLDVT 2005: 19-26 - [c23]Juan-Carlos Ruiz-Garcia, José Carlos Campelo, Pedro J. Gil, Juan Pardo:
On-chip Debugging-based Fault Emulation for Robustness Evaluation of Embedded Software Components. PRDC 2005: 57-64 - 2004
- [c22]Sara Blanc, Joaquin Gracia, Pedro J. Gil:
Experiences during the Experimental Validation of the Time-Triggered Architecture. DATE 2004: 256-261 - [c21]Juan-Carlos Ruiz-Garcia, Pedro Yuste, Pedro J. Gil, Lenin Lemus:
On Benchmarking the Dependability of Automotive Engine Control Applications. DSN 2004: 857-866 - [c20]Daniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil:
Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques. HLDVT 2004: 173-178 - 2003
- [j4]Daniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil:
Study, comparison and application of different VHDL-based fault injection techniques for the experimental validation of a fault-tolerant system. Microelectron. J. 34(1): 41-51 (2003) - [c19]Pedro Yuste, David de Andrés, Lenin Lemus, Juan José Serrano, Pedro J. Gil:
INERTE: Integrated NExus-Based Real-Time Fault Injection Tool for Embedded Systems. DSN 2003: 669 - [c18]Pedro Yuste, Juan-Carlos Ruiz-Garcia, Lenin Lemus, Pedro J. Gil:
Non-intrusive Software-Implemented Fault Injection in Embedded Systems. LADC 2003: 23-38 - [c17]Sara Blanc, Pedro J. Gil:
Improving the Multiple Errors Detection Coverage in Distributed Embedded Systems. SRDS 2003: 303- - 2002
- [j3]Juan Carlos Baraza, Joaquin Gracia, Daniel Gil, Pedro J. Gil:
A prototype of a VHDL-based fault injection tool: description and application. J. Syst. Archit. 47(10): 847-867 (2002) - [c16]Sara Blanc, Joaquin Gracia, Pedro J. Gil:
A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques. DFT 2002: 254-262 - [c15]Joaquin Gracia, Daniel Gil, Juan Carlos Baraza, Pedro J. Gil:
Using VHDL-Based Fault Injection to exercise Error Detection Mechanisms in the Time-Triggered Architecture. PRDC 2002: 316-320 - 2001
- [c14]Joaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil:
Comparison and Application of Different VHDL-Based Fault Injection Techniques. DFT 2001: 233-241 - [c13]Joaquin Gracia, Juan Carlos Baraza, Daniel Gil, Pedro J. Gil:
A Study of the Experimental Validation of Fault-Tolerant Systems Using Different VHDL-Based Fault Injection Techniques. IOLTW 2001: 140 - 2000
- [j2]José V. Busquets-Mataix, Daniel Gil, Pedro J. Gil, Andy J. Wellings:
Techniques to increase the schedulable utilization of cache-based preemptive real-time systems. J. Syst. Archit. 46(4): 357-378 (2000) - [c12]Juan Carlos Baraza, Joaquin Gracia, Daniel Gil, Pedro J. Gil:
A Prototype of a VHDL-Based Fault Injection Tool. DFT 2000: 396-404 - [c11]Lenin Lemus, David de Andrés, Pedro J. Gil:
An alternative to unify performance and reliability analysis of industrial applications. ESM 2000: 326-330 - [c10]Daniel Gil, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil:
A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System. IOLTW 2000: 73-79
1990 – 1999
- 1999
- [j1]José Carlos Campelo, Francisco Rodríguez, Alicia Rubio, Rafael Ors, Pedro J. Gil, Lenin Lemus, J. V. Busquets, José Albaladejo, Juan José Serrano:
Distributed industrial control systems: a fault-tolerant architecture. Microprocess. Microsystems 23(2): 103-112 (1999) - [c9]Daniel Gil, R. Martínez, J. V. Busquets, Juan Carlos Baraza, Pedro J. Gil:
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System. EDCC 1999: 191-208 - [c8]José Carlos Campelo, Pedro Yuste, Francisco Rodríguez, Pedro J. Gil, Juan José Serrano:
Dependability Evaluation of Fault Tolerant Distributed Industrial Control Systems. IPPS/SPDP Workshops 1999: 384-388 - [c7]José Carlos Campelo, Pedro Yuste, Francisco Rodríguez, Pedro J. Gil, Juan José Serrano:
Hierarchical Reliability and Safety Models of Fault Tolerant Distributed Industrial Control Systems. SAFECOMP 1999: 202-215 - [c6]José Carlos Campelo, Francisco Rodríguez, Pedro J. Gil, Juan José Serrano:
Design and Validation of a Distributed Industrial Control System's Nodes. SRDS 1999: 300-301 - 1998
- [c5]Daniel Gil, Juan Carlos Baraza, J. V. Busquets, Pedro J. Gil:
Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System. EUROMICRO 1998: 10418-10425 - 1996
- [c4]José V. Busquets-Mataix, Juan José Serrano, Rafael Ors Carot, Pedro J. Gil, Andrew J. Wellings:
Adding Instruction Cache Effect to an Exact Schedulability Analysis of Preemptive Real-Time Systems. RTS 1996: 271-276 - [c3]Vicente Santonja, Marina Alonso, Xavier Molero, Juan José Serrano, Pedro J. Gil, Rafael Ors:
Dependability Models of RAID Using Stochastic Activity Networks. EDCC 1996: 141-158 - [c2]José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings:
Adding instruction cache effect to schedulability analysis of preemptive real-time systems. IEEE Real Time Technology and Applications Symposium 1996: 204-212 - [c1]José V. Busquets-Mataix, Juan José Serrano, Rafael Ors, Pedro J. Gil, Andy J. Wellings:
Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems. RTCSA 1996: 195-202
Coauthor Index
Juan Carlos Baraza
aka: Juan-Carlos Baraza-Calvo
aka: Juan-Carlos Baraza-Calvo
Daniel Gil
aka: Daniel Gil-Tomas
aka: Daniel Gil-Tomas
Joaquin Gracia
aka: Joaquin Gracia-Moran
aka: Joaquin Gracia-Moran
Luis J. Saiz
aka: Luis J. Saiz-Adalid
aka: Luis J. Saiz-Adalid
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