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ORCIDDaisuke Kurose
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2010 – 2019
- 2019
[j12]Kentaro Yoshioka
, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura:
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits. IEEE Trans. Very Large Scale Integr. Syst. 27(11): 2575-2586 (2019)- 2018
- [j11]Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto:
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. IEEE J. Solid State Circuits 53(11): 3026-3038 (2018) - [c8]Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiro Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto:
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. ISSCC 2018: 92-94 - 2017
- [c7]Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura:
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique. ISSCC 2017: 478-479 - 2016
- [c6]Junya Matsuno, Daisuke Kurose, Tomohiko Sugimoto, Hirotomo Ishii, Masanori Furuta, Tetsuro Itakura:
A power-scalable zero-crossing-based amplifier using inverter-based zero-crossing detector with CMFB. ISCAS 2016: 482-485 - 2014
- [c5]Kei Shiraishi, Daisuke Kurose, Masanori Furuta, Tetsuro Itakura:
A power supply noise cancellation scheme for a 2.24-GHz 6-bit current-steering DAC. ISCAS 2014: 1151-1154 - 2013
- [j10]Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa:
Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication". IEEE J. Solid State Circuits 48(6): 1540 (2013) - 2012
- [j9]Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa:
A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication. IEEE J. Solid State Circuits 47(12): 3160-3171 (2012) - [c4]Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa:
A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication. ISSCC 2012: 266-268 - [c3]Daisuke Miyashita, Kenichi Agawa, Hirotsugu Kajihara, Kenichi Sami, Masaomi Iwanaga, Yosuke Ogasawara, Tomohiko Ito, Daisuke Kurose, Naotaka Koide, Toru Hashimoto, Hiroki Sakurai, Takafumi Yamaji, Takashi Kurihara, Kazumi Sato, Ichiro Seto, Hiroshi Yoshida, Ryuichi Fujimoto, Yasuo Unekawa:
A -70dBm-sensitivity 522Mbps 0.19nJ/bit-TX 0.43nJ/bit-RX transceiver for TransferJet™ SoC in 65nm CMOS. VLSIC 2012: 74-75
2000 – 2009
- 2008
- [j8]Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 454-460 (2008) - [j7]Akihide Sai, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(2): 557-560 (2008) - [j6]Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW, 1.2-V, 12-bit, 100-MSPS Pipeline ADCs for Wireless Receivers. IEICE Trans. Electron. 91-C(6): 887-893 (2008) - 2006
- [j5]Tomohiko Ito, Daisuke Kurose, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
Low-Power Design of 10-bit 80-MSPS Pipeline ADCs. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(7): 2003-2008 (2006) - [j4]Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. IEEE J. Solid State Circuits 41(7): 1589-1595 (2006) - [c2]Takeshi Ueno, Tomohiko Ito, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 1.2 V, 24 mW/ch, 10 bit, 80 MSample/s Pipelined A/D Converters. CICC 2006: 501-504 - 2005
- [j3]Tomohiko Ito, Takeshi Ueno, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura:
A 10-bit, 200-MSPS, 105-mW pipeline A-to-D converter. IEICE Electron. Express 2(15): 429-433 (2005) - [c1]Daisuke Kurose, Tomohiko Ito, Takeshi Ueno, Takafumi Yamaji, Tetsuro Itakura:
55-mW 200-MSPS 10-bit pipeline ADCs for wireless receivers. ESSCIRC 2005: 527-530 - 2004
- [j2]Tomohiko Ito, Takafumi Yamaji, Daisuke Kurose, Tetsuro Itakura:
Capacitance Mismatch Evaluation for Low-power Pipeline ADC Design. IEICE Electron. Express 1(3): 63-68 (2004) - 2003
- [j1]Takafumi Yamaji, Daisuke Kurose, Osamu Watanabe, Shuichi Obayashi, Tetsuro Itakura:
A four-input beam-forming downconverter for adaptive antennas. IEEE J. Solid State Circuits 38(10): 1619-1625 (2003)
Coauthor Index
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