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Masayuki Ito
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2020 – today
- 2023
- [c16]Masayuki Ito:
Architecture Challenges for Heterogeneous Processors in Embedded SoCs. A-SSCC 2023: 1-2 - 2020
- [c15]Natsuki Matsunami, Masayuki Ito, Sotaro Karakama:
Architecture and Interface for Collaborating with a Group of Agents in an Adversarial Game. IIAI-AAI 2020: 499-505
2010 – 2019
- 2018
- [c14]Andrew Dornbush, Karthik Vijayakumar, Sameer Bardapurkar, Fahad Islam, Masayuki Ito, Maxim Likhachev:
A Single-Planner Approach to Multi-Modal Humanoid Mobility. ICRA 2018: 1-9 - 2017
- [c13]Hayato Kimura, Hideyuki Noda, Hisaaki Watanabe, Takashi Higuchi, Ryosaku Kobayashi, Masayuki Utsuno, Fumitake Takami, Sugako Otani, Masayuki Ito, Yasuhisa Shimazaki, Naoki Yada, Hiroyuki Kondo:
3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEV. ISSCC 2017: 58-59 - 2013
- [c12]Yoshiyuki Doi, Manabu Oguma, Masayuki Ito, Ikuo Ogawa, Toshihide Yoshimatsu, Tetsuichiro Ohno, Eiji Yoshida, Hiroshi Takahashi:
Compact ROSA for 100-Gb/s (4 × 25 Gb/s) Ethernet with a PLC-based AWG demultiplexer. OFC/NFOEC 2013: 1-3 - 2011
- [j6]Osamu Nishii, Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Yasutaka Wada
, Keiji Kimura, Hironori Kasahara
, Hideo Maejima:
A 45-nm 37.3 GOPS/W Heterogeneous Multi-Core SOC with 16/32 Bit Instruction-Set General-Purpose Core. IEICE Trans. Electron. 94-C(4): 663-669 (2011) - 2010
- [c11]Yoichi Yuyama, Masayuki Ito, Yoshikazu Kiyoshige, Yusuke Nitta, Shigezumi Matsui, Osamu Nishii, Atsushi Hasegawa, Makoto Ishikawa, Tetsuya Yamada, Junichi Miyakoshi, Koichi Terada, Tohru Nojiri, Masashi Satoh, Hiroyuki Mizuno
, Kunio Uchiyama, Yasutaka Wada
, Keiji Kimura, Hironori Kasahara
, Hideo Maejima:
A 45nm 37.3GOPS/W heterogeneous multi-core SoC. ISSCC 2010: 100-101
2000 – 2009
- 2009
- [j5]Masayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama:
A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU. IEEE J. Solid State Circuits 44(1): 83-89 (2009) - [j4]Tohru Nojiri, Yuki Kondo, Naohiko Irie, Masayuki Ito, Hajime Sasaki, Hideo Maejima:
Domain Partitioning Technology for Embedded Multicore Processors. IEEE Micro 29(6): 7-17 (2009) - [c10]Tatsuya Kamei, Tetsuhiro Yamada, Takao Koike, Masayuki Ito, Takahiro Irita, Kenichi Nitta, Toshihiro Hattori, Shinichi Yoshioka:
A 65nm dual-mode baseband and multimedia application processor SoC with advanced power and memory management. ASP-DAC 2009: 535-539 - [c9]Masafumi Onouchi, Keisuke Toyama, Tohru Nojiri, Makoto Sato, Masayoshi Mase, Jun Shirako, Mikiko Sato, Masashi Takada, Masayuki Ito, Hiroyuki Mizuno
, Mitaro Namiki, Keiji Kimura, Hironori Kasahara
:
Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. ICPP 2009: 510-517 - 2008
- [c8]Hideyuki Tsukagoshi, Ato Kitagawa, Masayuki Ito, Kuniaki Ooe, Ichiro Kiryu, T. Kochiya:
Bari-bari-II: Jack-up rescue robot with debris opening function. ICRA 2008: 2209-2210 - [c7]Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno
, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara
:
An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler. ISSCC 2008: 90-91 - 2007
- [c6]Masayuki Ito, Toshihiro Hattori, Takahiro Irita, Ken Tatezawa, Fumihito Tanaka, Kenji Hirose, Shinichi Yoshioka, Koji Ohno, Reiko Tsuchihashi, Minoru Sakata, Masayuki Yamamoto, Yuji Aral:
A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS. ISSCC 2007: 274-602 - 2006
- [c5]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Yoshihiko Yasu, Tadashi Hoshi, Yujiro Miyairi, Kazumasa Yanagisawa, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Toshifumi Ishii, Yusuke Kanno, Hiroyuki Mizuno, Tetsuya Yamada, Naohiko Irie, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
Hierarchical power distribution and power management scheme for a single chip mobile processor. DAC 2006: 292-295 - [c4]Masayuki Ito, Takahiro Irita, Eiji Yamamoto, Kunihiko Nishiyama, Takao Koike, Yoshihiko Tsuchihashi, Hiroyuki Asano, Hiroshi Yagi, Saneaki Tamaki, Ken Tatezawa, Toshihiro Hattori, Shinichi Yoshioka, Koji Ohno:
SH-MobileG1: A single-chip application and dual-mode baseband processor. Hot Chips Symposium 2006: 1-24 - [c3]Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. ISSCC 2006: 2210-2219 - 2003
- [c2]Masayuki Ito, David G. Chinnery
, Kurt Keutzer:
Low Power Multiplication Algorithm for Switching Activity Reduction through Operand Decomposition. ICCD 2003: 21-
1990 – 1999
- 1997
- [j3]Masayuki Ito, Naofumi Takagi
, Shuzo Yajima:
Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification. IEEE Trans. Computers 46(4): 495-498 (1997) - 1996
- [j2]Masayuki Ito, Naofumi Takagi
, Shuzo Yajima:
Square Rooting by Iterative Multiply-Additions. Inf. Process. Lett. 60(5): 267-269 (1996) - 1995
- [c1]Masayuki Ito, Naofumi Takagi, Shuzo Yajima:
Efficient Initial Approximation and Fast Converging Methods for Division and Square Root. IEEE Symposium on Computer Arithmetic 1995: 2-8 - 1990
- [j1]Nagisa Ishiura, Masayuki Ito, Shuzo Yajima:
Dynamic two-dimensional parallel simulation technique for high-speed fault simulation on a vector processor. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(8): 868-875 (1990)
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