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Aditya Sankar Medury
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2020 – today
- 2023
- [j5]Manas Pratap
, Harshit Kansal
, Aditya Sankar Medury:
Analysis and Mitigation of Negative Differential Resistance effects in Double-Gate Silicon-on-Insulator Negative Capacitance Field Effect Transistor with improved analog performance. Microelectron. J. 136: 105777 (2023) - [j4]Harshit Kansal
, Aditya Sankar Medury:
Engineering negative capacitance Fully Depleted Silicon-on-insulator FET for improved performance. Microelectron. J. 140: 105917 (2023) - 2022
- [j3]Harshit Kansal
, Aditya Sankar Medury
:
FE/PE/DE gate stack enabling improved analog performance in partially Junction-less NCFETs. Microelectron. J. 128: 105571 (2022)
2010 – 2019
- 2018
- [i1]Offer Grembek, Alex A. Kurzhanskiy, Aditya Sankar Medury, Pravin Varaiya, Mengqiao Yu:
An Intelligent Intersection. CoRR abs/1803.00471 (2018) - 2016
- [j2]Aditya Sankar Medury, K. N. Bhat, Navakanta Bhat:
Impact of carrier quantum confinement on the short channel effects of double-gate silicon-on-insulator FINFETs. Microelectron. J. 55: 143-151 (2016) - 2015
- [j1]Aditya Sankar Medury, Weizeng Zhang, Pablo L. Durango-Cohen:
Identification and estimation of latent group-level-effects in infrastructure performance modeling. EURO J. Transp. Logist. 4(1): 31-55 (2015) - [c2]Juan Pablo Duarte, Sourabh Khandelwal
, Aditya Sankar Medury, Chenming Hu, Pragya Kushwaha, Harshit Agarwal, Avirup Dasgupta, Yogesh Singh Chauhan
:
BSIM-CMG: Standard FinFET compact model for advanced circuit design. ESSCIRC 2015: 196-201 - 2013
- [b1]Aditya Sankar Medury:
Incorporating Network Considerations into System-level Pavement Management Systems. University of California, Berkeley, USA, 2013
2000 – 2009
- 2005
- [c1]Aditya Sankar Medury, Ingvar Carlson, Atila Alvandpour, John Stensby:
Structural Fault Diagnosis in Charge-Pump Based Phase-Locked Loops. VLSI Design 2005: 842-845
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last updated on 2024-06-10 20:27 CEST by the dblp team
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