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ORCIDVenkatram Krishnaswamy
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2010 – 2019
- 2016
[j4]Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa:
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor. IEEE J. Solid State Circuits 51(1): 79-91 (2016)- 2015
- [c14]Venkatram Krishnaswamy, Jeffrey Brooks, Georgios K. Konstadinidis, Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang:
4.3 Fine-grained adaptive power management of the SPARC M7 processor. ISSCC 2015: 1-3 - [c13]Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister:
4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor. ISSCC 2015: 1-3 - 2014
- [j3]Jason Hart, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Venkatram Krishnaswamy, Lance Kwong, Robert P. Masleid, Rakesh Mehta, Umesh Nawathe, Aparna Ramachandran, Harikaran Sathianathan, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen:
A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm. IEEE J. Solid State Circuits 49(1): 19-31 (2014) - [c12]Yifan YangGong, Sebastian Turullols, Daniel Woo, Changku Huang, King C. Yen, Venkatram Krishnaswamy, Kalon Holdbrook, Jinuk Luke Shin:
Asymmetric Frequency Locked Loop (AFLL) for adaptive clock generation in a 28nm SPARC M6 processor. A-SSCC 2014: 373-376 - 2013
- [c11]Venkatram Krishnaswamy, Dawei Huang, Sebastian Turullols, Jinuk Luke Shin:
Bandwidth and power management of glueless 8-socket SPARC T5 system. ISSCC 2013: 58-59
2000 – 2009
- 2002
- [j2]Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee:
Automatic Parallelization of Compiled Event Driven VHDL Simulation. IEEE Trans. Computers 51(4): 380-394 (2002) - 2001
- [c10]Venkatram Krishnaswamy, A. B. Ma, Praveen Vishakantaiah:
A study of bridging defect probabilities on a Pentium (TM) 4 CPU. ITC 2001: 688-695 - 2000
- [c9]Venkatram Krishnaswamy, Jeremy Casas, Thomas Tetzlaff:
A switch level fault simulation environment. DAC 2000: 780-785
1990 – 1999
- 1998
- [c8]Dhruva R. Chakrabarti, Pramod G. Joisha, John A. Chandy
, Krishnaswamy Krishnaswamy, Venkatram Krishnaswamy, Prithviraj Banerjee:
WADE: a Web-based automated parallel CAD environment. HiPC 1998: 473-480 - [c7]Venkatram Krishnaswamy, Prithviraj Banerjee:
Parallel Compiled Event Driven VHDL Simulation. International Conference on Supercomputing 1998: 297-304 - 1997
- [b1]Venkatram Krishnaswamy:
Parallel Algorithms for VHDL Simulation. University of Illinois Urbana-Champaign, USA, 1997 - [j1]Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee:
Implications of VHDL timing models on simulation and software synthesis. J. Syst. Archit. 44(1): 23-36 (1997) - [c6]Venkatram Krishnaswamy, Rajesh Gupta, Prithviraj Banerjee:
A procedure for software synthesis from VHDL models. ASP-DAC 1997: 593-598 - [c5]Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee:
Load Balancing and Workload Minimization Of Overlapping Parallel Tasks. ICPP 1997: 272-279 - [c4]John G. Holm, John A. Chandy, Steven Parkes, Sumit Roy, Venkatram Krishnaswamy, Gagan Hasteer, Prithviraj Banerjee:
Performance Evaluation of Message-Driven Parallel VLSI CAD Applications on General Purpose Multiprocessors. International Conference on Supercomputing 1997: 172-179 - 1996
- [c3]Venkatram Krishnaswamy, Prithviraj Banerjee:
Actor Based Parallel VHDL Simulation Using Time Warp. Workshop on Parallel and Distributed Simulation 1996: 135-142 - 1995
- [c2]Lantz Moore, Debra A. Hensgen, David Charley, Venkatram Krishnaswamy, Dale E. Martin, Timothy J. McBrayer, Philip A. Wilsey:
graze: A Tool for Performance Visualization and Analysis. ICPP (2) 1995: 135-138 - [c1]Sidharta Mohanty, Venkatram Krishnaswamy, Philip A. Wilsey:
System Modeling, Performance Analysis, and Evolutionary Prototyping with Hardware Description Languages. MASCOTS 1995: 312-318
Coauthor Index
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