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2020 – today
- 2020
[j32]Khalifa M. Bellazi
, Rodrigo Marino, José Manuel Lanza-Gutiérrez, Teresa Riesgo:
Towards an Machine Learning-Based Edge Computing Oriented Monitoring System for the Desert Border Surveillance Use Case. IEEE Access 8: 218304-218322 (2020)
2010 – 2019
- 2019
- [j31]Sergio Quintero, Rodrigo Marino, José Manuel Lanza-Gutiérrez, Francisco Javier Sanza, Teresa Riesgo, Miguel Holgado:
A Novel Data Processing Technique for Expert Resonant Nano-Pillars Transducers: A Case Study Measuring Ethanol in Water and Wine Liquid Matrices. IEEE Access 7: 129778-129788 (2019) - [c61]Rodrigo Marino, Sergio Quintero, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Miguel Holgado, Jorge Portilla, Eduardo de la Torre:
Hardware Accelerator for Ethanol Detection in Water Media based on Machine Learning Techniques. DCIS 2019: 1-6 - 2018
- [j30]Alfonso Rodríguez, Juan Valverde, Jorge Portilla, Andrés Otero, Teresa Riesgo, Eduardo de la Torre:
FPGA-Based High-Performance Embedded Systems for Adaptive Edge Computing in Cyber-Physical Systems: The ARTICo3 Framework. Sensors 18(6): 1877 (2018) - [j29]Gabriel Mujica, Roberto Rodriguez-Zurrunero, Mark Richard Wilby, Jorge Portilla, Ana Belén Rodríguez-González, Álvaro Araujo, Teresa Riesgo, Juan José Vinagre-Díaz:
Edge and Fog Computing Platform for Data Fusion of Complex Heterogeneous Sensors. Sensors 18(11): 3630 (2018) - [c60]Jose Angel Miranda Calero, Rodrigo Marino, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Mario García-Valderas, Celia López-Ongil:
Embedded Emotion Recognition within Cyber-Physical Systems using Physiological Signals. DCIS 2018: 1-6 - [c59]Jaime Zornoza, Gabriel Mujica, Jorge Portilla, Teresa Riesgo:
Poster: Smart Self-Adaptive Clustering Technique for Collaborative Sensing in IoT Risk Contexts. EWSN 2018: 187-188 - [c58]Rodrigo Marino, José Manuel Lanza-Gutiérrez, Teresa Riesgo, Miguel Holgado:
Design Space Exploration for PCA Implementation of Embedded Learning in FPGAs. ISCAS 2018: 1-5 - 2016
- [j28]Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Teresa Riesgo, Roberto Sarmiento:
A scalable H.264/AVC deblocking filter architecture. J. Real Time Image Process. 12(1): 81-105 (2016) - [j27]Yaseer Arafat Durrani, Teresa Riesgo:
Efficient power analysis approach and its application to system-on-chip design. Microprocess. Microsystems 46: 11-20 (2016) - [j26]Christos P. Antonopoulos, Katerina Asimogloy, Sarah Chiti, Luca D'Onofrio, Simone Gianfranceschi, Danping He, Antonio Iodice, Stavros A. Koubias, Christos Koulamas, Luciano Lavagno, Mihai T. Lazarescu, Gabriel Mujica, George D. Papadopoulos, Jorge Portilla, Luis M. Redondo, Daniele Riccio, Teresa Riesgo, Daniel Rodríguez, Giuseppe Ruello, Vasilis Samoladas, Tsenka Stoyanova, Gerasimos Touliatos, Angela Valvo, Georgia Vlahoy:
Integrated Toolset for WSN Application Planning, Development, Commissioning and Maintenance: The WSN-DPCM ARTEMIS-JU Project. Sensors 16(6): 804 (2016) - 2015
- [j25]Danping He, Gabriel Mujica, Jorge Portilla, Teresa Riesgo:
Modelling and planning reliable wireless sensor networks based on multi-objective optimization genetic algorithm with changeable length. J. Heuristics 21(2): 257-300 (2015) - [j24]Wei Li, Jorge Portilla, Félix Moreno, Guixuan Liang, Teresa Riesgo:
Multiple feature points representation in target localization of wireless visual sensor networks. J. Netw. Comput. Appl. 57: 119-128 (2015) - [j23]Eduardo de la Torre, Jorge Portilla, Teresa Riesgo:
Letter from the guest editors of the special issue on DCIS 2014. Microprocess. Microsystems 39(8): 919 (2015) - [j22]Gabriel Mujica, Jorge Portilla, Teresa Riesgo:
Performance evaluation of an AODV-based routing protocol implementation by using a novel in-field WSN diagnosis tool. Microprocess. Microsystems 39(8): 920-938 (2015) - [c57]Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre:
Adaptive reconfigurable voting for enhanced reliability in medium-grained fault tolerant architectures. AHS 2015: 1-8 - [c56]Gabriel Mujica, Alejandro Garcia, Javier Gordillo, Jorge Portilla, Teresa Riesgo:
A novel on-site deployment, commissioning and debugging technique to assess and validate WSN based smart systems. ISCAS 2015: 1722-1725 - [c55]Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Live demonstration: A dynamically adaptable image processing application running in an FPGA-based WSN platform. ISCAS 2015: 1902 - [c54]Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Fast and compact evolvable systolic arrays on dynamically reconfigurable FPGAs. ReCoSoC 2015: 1-7 - [c53]Alfonso Rodríguez, Juan Valverde, Cesar Castanares, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Execution modeling in self-aware FPGA-based architectures for efficient resource management. ReCoSoC 2015: 1-8 - 2014
- [j21]Yaseer Arafat Durrani, Teresa Riesgo:
High-Level Power Analysis for Intellectual Property-Based Digital Systems. Circuits Syst. Signal Process. 33(4): 1035-1051 (2014) - [j20]Yaseer Arafat Durrani, Teresa Riesgo:
Power estimation for intellectual property-based digital systems at the architectural level. J. King Saud Univ. Comput. Inf. Sci. 26(3): 287-295 (2014) - [j19]Danping He, Gabriel Mujica, Guixuan Liang, Jorge Portilla, Teresa Riesgo:
Radio propagation modeling and real test of ZigBee based indoor wireless sensor networks. J. Syst. Archit. 60(9): 711-725 (2014) - [j18]Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Customized and automated routing repair toolset towards side-channel analysis resistant dual rail logic. Microprocess. Microsystems 38(8): 899-910 (2014) - [c52]Blanca López, Juan Valverde, Eduardo de la Torre, Teresa Riesgo:
Power-aware multi-objective evolvable hardware system on an FPGA. AHS 2014: 61-68 - [c51]Filip Veljkovic, Teresa Riesgo, Eduardo de la Torre, Raul Regada, Luis Berrojo:
A run time adaptive architecture to trade-off performance for fault tolerance applied to a DVB on-board processor. AHS 2014: 143-150 - [c50]Juan Valverde, Alfonso Rodríguez, Julio Camarero, Andrés Otero, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems. FPL 2014: 1-4 - [c49]Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo:
Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. ReCoSoC 2014: 1-7 - 2013
- [j17]Yaseer Arafat Durrani, Teresa Riesgo:
High-Level Power Analysis for Intellectual Property-Based Digital Systems. J. Low Power Electron. 9(4): 435-444 (2013) - [j16]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Self-Reconfigurable Evolvable Hardware System for Adaptive Image Processing. IEEE Trans. Computers 62(8): 1481-1493 (2013) - [c48]Javier Mora, Angel Gallego, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Noise-agnostic adaptive image filtering without training references on an evolvable hardware platform. DASIP 2013: 182-189 - [c47]Javier Mora, Angel Gallego, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A noise-agnostic self-adaptive image processing application based on evolvable hardware. DASIP 2013: 351-352 - [c46]Angel Gallego, Javier Mora, Andrés Otero, Blanca López, Eduardo de la Torre, Teresa Riesgo:
A self-adaptive image processing application based on evolvable and scalable hardware. FPL 2013: 1 - [c45]Danping He, Jorge Portilla, Teresa Riesgo:
A 3D multi-objective optimization planning algorithm for wireless sensor networks. IECON 2013: 5428-5433 - [c44]Gabriel Mujica, Victor Rosello, Jorge Portilla, Teresa Riesgo:
On-the-fly dynamic reprogramming mechanism for increasing the energy efficiency and supporting multi-experimental capabilities in WSNs. IECON 2013: 5455-5460 - [c43]Angel Gallego, Javier Mora, Andrés Otero, Rubén Salvador, Eduardo de la Torre, Teresa Riesgo:
A Novel FPGA-based Evolvable Hardware System Based on Multiple Processing Arrays. IPDPS Workshops 2013: 182-191 - [c42]Angel Gallego, Javier Mora, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
A scalable evolvable hardware processing array. ReConFig 2013: 1-7 - 2012
- [j15]Juan Valverde, Victor Rosello, Gabriel Mujica, Jorge Portilla, Amaia Uriarte, Teresa Riesgo:
Wireless Sensor Network for Environmental Monitoring: Application in a Coffee Factory. Int. J. Distributed Sens. Networks 8 (2012) - [j14]Rubén Salvador, Alberto Vidal, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
Accelerating FPGA-based evolution of wavelet transform filters by optimized task scheduling. Microprocess. Microsystems 36(5): 427-438 (2012) - [j13]Juan Valverde, Andrés Otero, Miguel Lopez, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Using SRAM Based FPGAs for Power-Aware High Performance Wireless Sensor Networks. Sensors 12(3): 2667-2692 (2012) - [c41]Wei He, Eduardo de la Torre, Teresa Riesgo:
An Interleaved EPE-Immune PA-DPL Structure for Resisting Concentrated EM Side Channel Attacks on FPGA Implementation. COSADE 2012: 39-53 - [c40]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Implementation techniques for evolvable HW systems: virtual VS. dynamic reconfiguration. FPL 2012: 547-550 - [c39]Guixuan Liang, Jorge Portilla, Teresa Riesgo:
Low-complexity timing synchronization scheme for MB-OFDM UWB receiver based on sign-bit. ICUWB 2012: 311-315 - [c38]Gabriel Mujica, Victor Rosello, Jorge Portilla, Teresa Riesgo:
Hardware-software integration platform for a WSN testbed based on cookies nodes. IECON 2012: 6013-6018 - [c37]Danping He, Gabriel Mujica, Jorge Portilla, Teresa Riesgo:
Simulation tool and case study for planning wireless sensor network. IECON 2012: 6024-6028 - [c36]Jihoon Yang, Jorge Portilla, Teresa Riesgo:
Smart parking service based on Wireless Sensor Networks. IECON 2012: 6029-6034 - [c35]Wei He, Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Automatic generation of identical routing pairs for FPGA implemented DPL logic. ReConFig 2012: 1-6 - [c34]Andrés Otero, Eduardo de la Torre, Teresa Riesgo:
Dreams: A tool for the design of dynamically reconfigurable embedded and modular systems. ReConFig 2012: 1-8 - [c33]Miguel Lombardo, Julio Camarero, Juan Valverde, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
Power management techniques in an FPGA-based WSN node for high performance applications. ReCoSoC 2012: 1-8 - [c32]Guixuan Liang, Danping He, Jorge Portilla, Teresa Riesgo:
A hardware in the loop design methodology for FPGA system and its application to complex functions. VLSI-DAT 2012: 1-4 - 2011
- [j12]Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
Evolutionary Approach to Improve Wavelet Transforms for Image Compression in Embedded Systems. EURASIP J. Adv. Signal Process. 2011 (2011) - [c31]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
Evolvable 2D computing matrix model for intrinsic evolution in commercial FPGAs with native reconfiguration support. AHS 2011: 184-191 - [c30]Andrés Otero, Rubén Salvador, Javier Mora, Eduardo de la Torre, Teresa Riesgo, Lukás Sekanina:
A fast Reconfigurable 2D HW core architecture on FPGAs for evolvable Self-Adaptive Systems. AHS 2011: 336-343 - [c29]Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Teresa Cervero, Sebastián López, Gustavo Marrero Callicó, Roberto Sarmiento:
Run-Time Scalable Architecture for Deblocking Filtering in H.264/AVC-SVC Video Codecs. FPL 2011: 369-375 - [c28]Teresa Cervero, Andrés Otero, Sebastián López, Eduardo de la Torre, Gustavo Marrero Callicó, Roberto Sarmiento, Teresa Riesgo:
A novel scalable Deblocking Filter architecture for H.264/AVC and SVC video codecs. ICME 2011: 1-6 - [c27]Rubén Salvador, Andrés Otero, Javier Mora, Eduardo de la Torre, Lukás Sekanina, Teresa Riesgo:
Fault Tolerance Analysis and Self-Healing Strategy of Autonomous, Evolvable Hardware Systems. ReConFig 2011: 164-169 - [c26]Wei He, Eduardo de la Torre, Teresa Riesgo:
A Precharge-Absorbed DPL Logic for Reducing Early Propagation Effects on FPGA Implementations. ReConFig 2011: 217-222 - 2010
- [j11]Jorge Portilla, Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Oliver Stecklina, Steffen Peter, Peter Langendörfer:
Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors. Int. J. Distributed Sens. Networks 6(1) (2010) - [j10]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Reconfigurable Networks on Chip: DRNoC architecture. J. Syst. Archit. 56(7): 293-302 (2010) - [c25]Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
Evolutionary design and optimization of Wavelet Transforms for image compression in embedded systems. AHS 2010: 171-178 - [c24]Andrés Otero, Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Generic Systolic Array for Run-Time Scalable Cores. ARC 2010: 4-16 - [c23]Andrés Otero, Angel Morales-Cas, Jorge Portilla, Eduardo de la Torre, Teresa Riesgo:
A Modular Peripheral to Support Self-Reconfiguration in SoCs. DSD 2010: 88-95 - [c22]Rubén Salvador, Félix Moreno, Teresa Riesgo, Lukás Sekanina:
High Level Validation of an Optimization Algorithm for the Implementation of Adaptive Wavelet Transforms in FPGAs. DSD 2010: 96-103 - [c21]Andrés Otero, Eduardo de la Torre, Teresa Riesgo, Yana Esteves Krasteva:
Run-Time Scalable Systolic Coprocessors for Flexible Multimedia SoPCs. FPL 2010: 70-76
2000 – 2009
- 2009
- [j9]Yaseer Arafat Durrani, Teresa Riesgo:
Power estimation technique for DSP architectures. Digit. Signal Process. 19(2): 213-219 (2009) - [j8]Félix Moreno, Jaime Alarcón, Rubén Salvador, Teresa Riesgo:
Reconfigurable Hardware Architecture of a Shape Recognition System Based on Specialized Tiny Neural Networks With Online Training. IEEE Trans. Ind. Electron. 56(8): 3253-3263 (2009) - 2008
- [j7]Felipe Machado, Yago Torroja, Teresa Riesgo:
A Binary Decision Diagram Structure for Probabilistic Switching Activity Estimation. J. Low Power Electron. 4(3): 247-262 (2008) - [j6]Almudena M. Sánchez, Roberto Prieto, Manuel Laso, Teresa Riesgo:
A Piezoelectric Minirheometer for Measuring the Viscosity of Polymer Microsamples. IEEE Trans. Ind. Electron. 55(1): 427-436 (2008) - [c20]Felipe Machado, Teresa Riesgo, Yago Torroja:
Disjoint Region Partitioning for Probabilistic Switching Activity Estimation at Register Transfer Level. PATMOS 2008: 399-408 - [c19]Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo:
A Fast Emulation-Based NoC Prototyping Framework. ReConFig 2008: 211-216 - 2007
- [j5]Eduardo Peña, Eduardo de la Torre, Angel de Castro, Teresa Riesgo:
A digital system to emulate wireless networks. IET Comput. Digit. Tech. 1(5): 444-450 (2007) - [j4]Yaseer Arafat Durrani, Teresa Riesgo:
Architectural Power Analysis for Intellectual Property-Based Digital System. J. Low Power Electron. 3(3): 271-279 (2007) - [c18]Yaseer Arafat Durrani, Teresa Riesgo:
LUT-Based Power Macromodeling Technique for DSP Architectures. ICECS 2007: 1416-1419 - [c17]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task Management. ISCAS 2007: 873-876 - [c16]Yaseer Arafat Durrani, Ana Abril, Teresa Riesgo:
Efficient Power Macromodeling Technique for IP-Based Digital System. ISCAS 2007: 1145-1148 - 2006
- [j3]José Bravo, Xavier Alamán, Teresa Riesgo:
Ubiquitous Computing and Ambient Intelligence: New Challenges for Computing. J. Univers. Comput. Sci. 12(3): 233-235 (2006) - [j2]Jorge Portilla, Angel de Castro, Eduardo de la Torre, Teresa Riesgo:
A Modular Architecture for Nodes in Wireless Sensor Networks. J. Univers. Comput. Sci. 12(3): 328-339 (2006) - [c15]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo, Didier Joly:
Virtex II FPGA Bitstream Manipulation: Application to Reconfiguration Control Systems. FPL 2006: 1-4 - [c14]Yaseer Arafat Durrani, Teresa Riesgo:
Power Macromodeling for IP Modules. ICECS 2006: 1172-1175 - [c13]Jorge Portilla, José Luis Buron, Teresa Riesgo, Angel de Castro:
A Hardware Library for Sensors/Actuators Interfaces in Sensor Networks. ICECS 2006: 1244-1247 - [c12]Yaseer Arafat Durrani, Teresa Riesgo, Felipe Machado:
Power estimation for register transfer level by genetic algorithm. ICINCO-RA 2006: 527-530 - [c11]Yaseer Arafat Durrani, Teresa Riesgo:
Power Estimation for IP-Based Modules. SoC 2006: 1-4 - [c10]Felipe Machado, Teresa Riesgo, Yago Torroja:
A Method for Switching Activity Analysis of VHDL-RTL Combinatorial Circuits. PATMOS 2006: 645-657 - [c9]Yana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo:
Partial Reconfiguration for Core Reallocation and Flexible Communications. ReCoSoC 2006: 91-97 - [c8]Yaseer Arafat Durrani, Teresa Riesgo:
Power Macromodeling for High Level Power Estimation. ReCoSoC 2006: 232-236 - 2005
- [c7]Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo:
Flexible Core Reallocation for Virtex II Structures. ERSA 2005: 189-195 - [c6]Felipe Machado, Teresa Riesgo, Yago Torroja:
Switching activity propagation of VHDL-RTL combinational designs through an automated tool. ICECS 2005: 1-4 - [c5]Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo:
Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. IEEE International Workshop on Rapid System Prototyping 2005: 77-83 - 2004
- [c4]Mario García-Valderas, Eduardo de la Torre, F. Ariza, Teresa Riesgo:
Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. FPL 2004: 1057-1061 - 2000
- [c3]Eduardo de la Torre, Teresa Riesgo, Javier Uceda, E. Macip, M. Rizzi:
Highly Configurable Control Boards: A Tool and a Design Experience. IEEE International Workshop on Rapid System Prototyping 2000: 174-
1990 – 1999
- 1999
- [j1]Teresa Riesgo, Yago Torroja, Eduardo de la Torre:
Design methodologies based on hardware description languages. IEEE Trans. Ind. Electron. 46(1): 3-12 (1999) - 1998
- [c2]Teresa Riesgo, Yago Torroja, Eduardo de la Torre, Javier Uceda:
Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models. DATE 1998: 955-956 - 1996
- [c1]Teresa Riesgo, Javier Uceda:
A fault model for VHDL descriptions at the register transfer level. EURO-DAC 1996: 462-467
Coauthor Index
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