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John Bainbridge
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2010 – 2019
- 2011
- [j6]Luis A. Plana, David M. Clark, Simon Davidson, Steve B. Furber, Jim D. Garside, Eustace Painkras, Jeffrey Pepper, Steve Temple, John Bainbridge:
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip. ACM J. Emerg. Technol. Comput. Syst. 7(4): 17:1-17:18 (2011)
2000 – 2009
- 2008
- [c5]Luis A. Plana, John Bainbridge, Steve B. Furber, Sean Salisbury, Yebin Shi, Jian Wu:
An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. NOCS 2008: 215-216 - 2007
- [c4]Andrew M. Scott, Mark E. Schuelein, Marly Roncken, Jin-Jer Hwan, John Bainbridge, John R. Mawer, David L. Jackson, Andrew Bardsley:
Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus. ASYNC 2007: 60-72 - 2005
- [j5]Aristides Efthymiou, John Bainbridge, Douglas A. Edwards:
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect. IEEE Trans. Very Large Scale Integr. Syst. 13(12): 1384-1393 (2005) - [c3]Steve B. Furber, John Bainbridge:
Future Trends in SoC Interconnect. SoC 2005 - 2004
- [j4]Stephen B. Furber, John Bainbridge, J. Mike Cumpstey, Steve Temple:
Sparse distributed memory using N-of-M codes. Neural Networks 17(10): 1437-1451 (2004) - [c2]Aristides Efthymiou, John Bainbridge, Douglas A. Edwards:
Adding Testability to an Asynchronous Interconnect for GALS SoC. Asian Test Symposium 2004: 20-23 - 2002
- [j3]John Bainbridge, Stephen B. Furber:
Chain: A Delay-Insensitive Chip Area Interconnect. IEEE Micro 22(5): 16-23 (2002)
1990 – 1999
- 1994
- [j2]John Bainbridge:
Defining Testability Metrics Axiomatically. Softw. Test. Verification Reliab. 4(2): 63-80 (1994) - 1992
- [j1]John Bainbridge:
A Heuristic Method for Generating Large Random Expressions. Inf. Process. Lett. 44(3): 165-170 (1992) - 1990
- [c1]John Bainbridge, Robin W. Whitty, John Wordsworth:
Obtaining Structural Metrics of Z Specifications for Systems Development. Z User Workshop 1990: 269-281
Coauthor Index
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