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2020 – today
- 2025
[j24]Franck Cappello
, Mario C. Acosta, Emmanuel Agullo, Hartwig Anzt, Jon Calhoun, Sheng Di, Luc Giraud, Thomas Grützmacher, Sian Jin, Kentaro Sano, Kento Sato, Amarjit Singh, Dingwen Tao, Jiannan Tian, Tomohiro Ueno, Robert Underwood, Frédéric Vivien, Xavier Yepes, Kazutomo Yoshii, Boyuan Zhang:
Multifacets of lossy compression for scientific data in the Joint-Laboratory of Extreme Scale Computing. Future Gener. Comput. Syst. 163: 107323 (2025)- 2024
- [j23]Juan Miguel De Haro Ruiz, Carlos Álvarez-Martínez, Daniel Jiménez-González, Xavier Martorell, Tomohiro Ueno, Kentaro Sano, Burkhard Ringlein, François Abel, Beat Weiss:
Automated parallel execution of distributed task graphs with FPGA clusters. Future Gener. Comput. Syst. 160: 808-824 (2024) - [j22]Andreas Koch, Kentaro Sano:
Introduction to the Special Issue on FPL 2022. ACM Trans. Reconfigurable Technol. Syst. 17(2): 19:1-19:3 (2024) - [j21]Emanuele Del Sozzo, Davide Conficconi, Kentaro Sano:
Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs. ACM Trans. Reconfigurable Technol. Syst. 17(2): 28:1-28:33 (2024) - [c70]Tomohiro Ueno, Emanuele Del Sozzo, Kentaro Sano:
Flexible Systolic Array Platform on Virtual 2-D Multi-FPGA Plane. HPC Asia 2024: 84-94 - [c69]Daiki Furukawa, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano:
HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator. ICCE 2024: 1-6 - [c68]Haruto Ikehara, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano:
A Productive HLS Simulation Approach for Multi-FPGA Systems. ICCE 2024: 1-2 - [c67]Kentaro Sano:
RAW 2024 Invited Talk-6: Reconfigurable Architectures for High-Performance Computing. IPDPS (Workshops) 2024: 88 - [c66]Emanuele Del Sozzo, Xinyuan Wang, Boma A. Adhi, Carlos Cortes, Jason Anderson, Kentaro Sano:
Exploration of Trade-offs Between General-Purpose and Specialized Processing Elements in HPC-Oriented CGRA. IPDPS 2024: 668-680 - 2023
- [j20]Philippos Papaphilippou, Kentaro Sano, Boma Anantasatya Adhi, Wayne Luk:
Experimental Survey of FPGA-Based Monolithic Switches and a Novel Queue Balancer. IEEE Trans. Parallel Distributed Syst. 34(5): 1621-1634 (2023) - [j19]Tomohiro Ueno, Kentaro Sano:
VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster. ACM Trans. Reconfigurable Technol. Syst. 16(2): 25:1-25:32 (2023) - [c65]Emanuele Del Sozzo, Davide Conficconi, Marco D. Santambrogio, Kentaro Sano:
Senju: A Framework for the Design of Highly Parallel FPGA-based Iterative Stencil Loop Accelerators. FPGA 2023: 233 - [c64]Emanuele Del Sozzo, Davide Conficconi, Kentaro Sano:
Journal Track Paper ICFPT 2023 : Across Time and Space: Senju's Approach for Scaling Iterative Stencil Loop Accelerators on Single and Multiple FPGAs. ICFPT 2023: 5 - [c63]Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase:
Performance Modeling and Scalability Analysis of Stream Computing in ESSPER FPGA Clusters. ICFPT 2023: 262-265 - [c62]Jason Anderson, Boma A. Adhi, Carlos Cortes, Emanuele Del Sozzo, Omar Ragheb, Kentaro Sano:
Exploration of Compute vs. Interconnect Tradeoffs in CGRAs for HPC. HEART 2023: 59-68 - [c61]Kentaro Sano, Atsushi Koshiba, Takaaki Miyajima, Tomohiro Ueno:
ESSPER: Elastic and Scalable FPGA-Cluster System for High-Performance Reconfigurable Computing with Supercomputer Fugaku. HPC Asia 2023: 140-150 - [c60]Boma A. Adhi, Carlos Cortes, Emanuele Del Sozzo, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano:
Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC. IPDPS Workshops 2023: 452-459 - [c59]Maximilian Jakob Heer, Emanuele Del Sozzo, Keisuke Fujii, Kentaro Sano:
Novel Union-Find-based Decoders for Scalable Quantum Error Correction on Systolic Arrays. IPDPS Workshops 2023: 524-533 - [c58]Maximilian Jakob Heer, Jan-Erik R. Wichmann, Kentaro Sano:
Achieving Scalable Quantum Error Correction with Union-Find on Systolic Arrays by Using Multi-Context Processing Elements. QCE 2023: 242-243 - [c57]Kazutomo Yoshii, Tomohiro Ueno, Kentaro Sano, Antonino Miceli, Franck Cappello:
Streaming Hardware Compressor Generator Framework. SC Workshops 2023: 289-297 - [c56]Kazutomo Yoshii, John R. Tramm, Bryce Allen, Tomohiro Ueno, Kentaro Sano, Andrew R. Siegel, Pete Beckman:
Hardware Specialization: Estimating Monte Carlo Cross-Section Lookup Kernel Performance and Area. SC Workshops 2023: 1274-1278 - 2022
- [c55]Boma A. Adhi, Carlos Cortes, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano:
The Cost of Flexibility: Embedded versus Discrete Routers in CGRAs for HPC. CLUSTER 2022: 347-356 - [c54]Boma A. Adhi, Carlos Cortes, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano:
Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage. FPT 2022: 1-4 - [c53]Ryota Miyagi, Ryota Yasudo, Kentaro Sano, Hideki Takase:
Elastic Sample Filter: An FPGA-based Accelerator for Bayesian Network Structure Learning. FPT 2022: 1 - [c52]Kentaro Sano, Atsushi Koshiba, Takaaki Miyajima, Tomohiro Ueno:
ESSPER: Elastic and Scalable System for High-Performance Reconfigurable Computing with Software-bridged APIs. FPT 2022: 1 - [c51]Tatsuma Mori, Daiki Furukawa, Keigo Motoyoshi, Haruto Ikehara, Kaito Ohira, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano:
Stream Computation of 3D Approximate Convex Hulls with an FPGA. HEART 2022: 69-75 - [c50]Tomohiro Ueno, Takaaki Miyajima, Kentaro Sano:
FPGA-Dedicated Network vs. Server Network for Pipelined Computing with Multiple FPGAs. HEART 2022: 90-91 - [c49]Satoshi Kaneko, Hiroyuki Takizawa, Kentaro Sano:
A SYCL-based high-level programming framework for HPC programmers to use remote FPGA clusters. HEART 2022: 92-94 - [c48]Artur Podobas, Kentaro Sano, Jason Anderson:
The First International Workshop on Coarse-Grained Reconfigurable Architectures for High-Performance Computing (CGRA4HPC). IPDPS Workshops 2022: 625-626 - [c47]Takuya Kojima, Boma A. Adhi, Carlos Cortes, Yiyu Tan, Kentaro Sano:
An Architecture- Independent CGRA Compiler enabling OpenMP Applications. IPDPS Workshops 2022: 631-638 - [c46]Boma A. Adhi, Carlos Cortes, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano:
Exploration Framework for Synthesizable CGRAs Targeting HPC: Initial Design and Evaluation. IPDPS Workshops 2022: 639-646 - 2021
- [c45]Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano:
Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA Cluster. ASAP 2021: 41-48 - [c44]Takaaki Miyajima, Kentaro Sano:
A memory bandwidth improvement with memory space partitioning for single-precision floating-point FFT on Stratix 10 FPGA. CLUSTER 2021: 787-790 - [c43]Philippos Papaphilippou, Kentaro Sano, Boma A. Adhi, Wayne Luk:
Efficient Queue-Balancing Switch for FPGAs. FPT 2021: 1-5 - 2020
- [j18]Artur Podobas, Kentaro Sano, Satoshi Matsuoka:
A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective. IEEE Access 8: 146719-146743 (2020) - [c42]Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, Hiroyuki Takizawa:
Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters. ARC 2020: 314-329 - [c41]Artur Podobas, Kentaro Sano, Satoshi Matsuoka:
A Template-based Framework for Exploring Coarse-Grained Reconfigurable Architectures. ASAP 2020: 1-8 - [c40]Jens Huthmann, Artur Podobas, Lukas Sommer, Andreas Koch, Kentaro Sano:
Extending High-Level Synthesis with High-Performance Computing Performance Visualization. CLUSTER 2020: 371-380 - [c39]Atsushi Koshiba, Kouki Watanabe, Takaaki Miyajima, Kentaro Sano:
Performance Evaluation and Power Analysis of Teraflop-scale Fluid Simulation with Stratix 10 FPGA. FPGA 2020: 321 - [c38]Norihisa Fujita, Ryohei Kobayashi, Yoshiki Yamaguchi, Tomohiro Ueno, Kentaro Sano, Taisuke Boku:
Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA. IPDPS Workshops 2020: 450-459 - [c37]Jens Huthmann, Lukas Sommer, Artur Podobas, Andreas Koch, Kentaro Sano:
OpenMP Device Offloading to FPGAs Using the Nymble Infrastructure. IWOMP 2020: 265-279 - [i6]Artur Podobas, Kentaro Sano, Satoshi Matsuoka:
A Survey on Coarse-Grained Reconfigurable Architectures from a Performance Perspective. CoRR abs/2004.04509 (2020) - [i5]Roman Iakymchuk, Daichi Mukunoki, Artur Podobas, Fabienne Jézéquel, Toshiyuki Imamura, Norihisa Fujita, Jens Huthmann, Shuhei Kudo, Yiyu Tan, Jens Domke, Kai Torben Ohlhus, Takeshi Fukaya, Takeo Hoshi, Yuki Murakami, Maho Nakata, Takeshi Ogita, Kentaro Sano, Taisuke Boku:
White Paper from Workshop on Large-scale Parallel Numerical Computing Technology (LSPANC 2020): HPC and Computer Arithmetic toward Minimal-Precision Computing. CoRR abs/2004.04628 (2020)
2010 – 2019
- 2019
- [j17]Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, Hiroyuki Takizawa:
Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs. IEICE Trans. Inf. Syst. 102-D(5): 1029-1036 (2019) - [c36]Yusuke Takaki, Kohei Nagasu, Shin Abiko, Minoru Watanabe, Kentaro Sano:
FPGA implementation of a robot control algorithm. ETFA 2019: 1571-1574 - [c35]Jens Huthmann, Shin Abiko, Artur Podobas, Kentaro Sano, Hiroyuki Takizawa:
Scaling Performance for N-Body Stream Computation with a Ring of FPGAs. HEART 2019: 10:1-10:6 - [c34]Takaaki Miyajima, Tomoya Hirao, Naoya Miyamoto, Jeongdo Son, Kentaro Sano:
A software bridged data transfer on a FPGA cluster by using pipelining and InfiniBand verbs. HEART 2019: 11:1-11:6 - [c33]Tomohiro Ueno, Takaaki Miyajima, Antoniette Mondigo, Kentaro Sano:
Hybrid Network Utilization for Efficient Communication in a Tightly Coupled FPGA Cluster. FPT 2019: 363-366 - [c32]Yuichi Kawamata, Tomohiro Kida, Yuichiro Shibata, Kentaro Sano:
Crossbar Implementation with Partial Reconfiguration for Stream Switching Applications on an FPGA. PARCO 2019: 721-730 - [c31]Tomohiro Kida, Yuichi Kawamata, Yuichiro Shibata, Kentaro Sano:
A High Level Synthesis Approach for Application Specific DMA Controllers. ReConFig 2019: 1-2 - 2018
- [j16]Tao Yu, Azril Haniz, Kentaro Sano, Ryosuke Iwata, Ryouta Kosaka, Yusuke Kuki, Gia Khanh Tran, Jun-ichi Takada, Kei Sakaguchi:
A Guide of Fingerprint Based Radio Emitter Localization Using Multiple Sensors. IEICE Trans. Commun. 101-B(10): 2104-2119 (2018) - [c30]Antoniette Mondigo, Kentaro Sano, Hiroyuki Takizawa:
Performance Estimation of Deeply Pipelined Fluid Simulation on Multiple FPGAs with High-speed Communication Subsystem. ASAP 2018: 1-4 - [c29]Tomohiro Ueno, Kentaro Sano, Takashi Furusawa:
Performance Analysis of Hardware-Based Numerical Data Compression on Various Data Formats. DCC 2018: 345-354 - [c28]Antoniette Mondigo, Kentaro Sano, Hiroyuki Takizawa:
Enhancing Memory Bandwidth in a Single Stream Computation with Multiple FPGAs. FPT 2018: 378-380 - [c27]Jinpil Lee, Tomohiro Ueno, Mitsuhisa Sato, Kentaro Sano:
High-productivity Programming and Optimization Framework for Stream Processing on FPGA. HEART 2018: 5:1-5:6 - [p1]Kentaro Sano, Hiroki Nakahara:
Hardware Algorithms. Principles and Structures of FPGAs 2018: 137-177 - [i4]Tao Yu, Azril Haniz, Kentaro Sano, Ryosuke Iwata, Ryouta Kosaka, Yusuke Kuki, Gia Khanh Tran, Jun-ichi Takada, Kei Sakaguchi:
A Guide of Fingerprint Based Radio Emitter Localization using Multiple Sensors. CoRR abs/1804.02124 (2018) - 2017
- [j15]Kohei Nagasu, Kentaro Sano, Fumiya Kono, Naohito Nakasato:
FPGA-based tsunami simulation: Performance comparison with GPUs, and roofline model for scalability analysis. J. Parallel Distributed Comput. 106: 153-169 (2017) - [j14]Kentaro Sano, Satoru Yamamoto:
FPGA-Based Scalable and Power-Efficient Fluid Simulation using Floating-Point DSP Blocks. IEEE Trans. Parallel Distributed Syst. 28(10): 2823-2837 (2017) - [j13]Tomohiro Ueno, Kentaro Sano, Satoru Yamamoto:
Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing. ACM Trans. Reconfigurable Technol. Syst. 10(3): 18:1-18:22 (2017) - [c26]Kentaro Sano, Shin Abiko, Tomohiro Ueno:
FPGA-based Stream Computing for High-Performance N-Body Simulation using Floating-Point DSP Blocks. HEART 2017: 16:1-16:6 - [c25]Antoniette Mondigo, Tomohiro Ueno, Daichi Tanaka, Kentaro Sano, Satoru Yamamoto:
Design and scalability analysis of bandwidth-compressed stream computing with multiple FPGAs. ReCoSoC 2017: 1-8 - 2016
- [c24]Kohei Nagasu, Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav G. Sedukhin:
Parallelism for High-Performance Tsunami Simulation with FPGA: Spatial or Temporal? FCCM 2016: 30 - 2015
- [j12]Kentaro Sano, Fumiya Kono, Naohito Nakasato, Alexander Vazhenin, Stanislav Sedukhin:
Stream Computation of Shallow Water Equation Solver for FPGA-based 1D Tsunami Simulation. SIGARCH Comput. Archit. News 43(4): 82-87 (2015) - [e2]Kentaro Sano, Dimitrios Soudris, Michael Hübner, Pedro C. Diniz:
Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings. Lecture Notes in Computer Science 9040, Springer 2015, ISBN 978-3-319-16213-3 [contents] - [i3]Kentaro Sano:
DSL-based Design Space Exploration for Temporal and Spatial Parallelism of Custom Stream Computing. CoRR abs/1509.00040 (2015) - 2014
- [j11]Kentaro Sano, Ryotaro Chiba, Tomoya Ueno, Hayato Suzuki, Ryo Ito, Satoru Yamamoto:
FPGA-based Custom Computing Architecture for Large-Scale Fluid Simulation with Building Cube Method. SIGARCH Comput. Archit. News 42(4): 45-50 (2014) - [j10]Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto:
Multi-FPGA Accelerator for Scalable Stencil Computation with Constant Memory Bandwidth. IEEE Trans. Parallel Distributed Syst. 25(3): 695-705 (2014) - [c23]Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto:
Bandwidth compression of multiple numerical data streams for high performance custom computing. ASAP 2014: 190-191 - [i2]Kentaro Sano, Hayato Suzuki, Ryo Ito, Tomohiro Ueno, Satoru Yamamoto:
Stream Processor Generator for HPC to Embedded Applications on FPGA-based System Platform. CoRR abs/1408.5386 (2014) - 2013
- [j9]Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Ryo Ito, Tomohiro Ueno, Kyo Koizumi, Satoru Yamamoto:
Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster. SIGARCH Comput. Archit. News 41(5): 47-52 (2013) - [c22]Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto:
Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-Based Custom Computing. ARC 2013: 90-102 - [c21]Kentaro Sano, Ryo Ito, Hayato Suzuki, Yoshiaki Kono:
Parallel and scalable custom computing for real-time fluid simulation on a cluster node with four tightly-coupled FPGAs. FPL 2013: 1 - 2012
- [j8]Khaled Benkrid, Esam El-Araby, Miaoqing Huang, Kentaro Sano, Thomas Steinke:
High-Performance Reconfigurable Computing. Int. J. Reconfigurable Comput. 2012: 104963:1-104963:2 (2012) - [j7]Kentaro Sano, Yoshiaki Kono:
FPGA-based Connect6 solver with hardware-accelerated move refinement. SIGARCH Comput. Archit. News 40(5): 4-9 (2012) - [c20]Luzhou Wang, Kentaro Sano, Satoru Yamamoto:
Domain-Specific Language and Compiler for Stencil Computation on FPGA-Based Systolic Computational-Memory Array. ARC 2012: 26-39 - [c19]Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto:
Scalability analysis of tightly-coupled FPGA-cluster for lattice Boltzmann computation. FPL 2012: 120-127 - [c18]Masayoshi Mase, Jun Okitsu, Eiichi Suzuki, Tohru Nojiri, Kentaro Sano, Hayato Shimizu:
Cooling efficiency aware workload placement using historical sensor data on IT-facility collaborative control. IGCC 2012: 1-6 - [c17]Kentaro Sano, Gia Khanh Tran, Masahiro Watanabe, Kei Sakaguchi, Kiyomichi Araki, Daisuke Hayashi, Toshihiro Yamaguchi, Shintaro Arata:
Multi-sensor location estimation for illegal cell-phone use in real-life indoor environment. ICCS 2012: 80-84 - [e1]Oliver C. S. Choy, Ray C. C. Cheung, Peter M. Athanas, Kentaro Sano:
Reconfigurable Computing: Architectures, Tools and Applications - 8th International Symposium, ARC 2012, Hong Kong, China, March 19-23, 2012. Proceedings. Lecture Notes in Computer Science 7199, Springer 2012, ISBN 978-3-642-28364-2 [contents] - [i1]Peter M. Athanas, Brad L. Hutchings, Kentaro Sano:
The NII Shonan Configurable Computing Workshop (NII Shonan Meeting 2012-11). NII Shonan Meet. Rep. 2012 (2012) - 2011
- [j6]Kentaro Sano, Satoru Yamamoto, Yoshiaki Hatsuda:
Domain-specific programmable design of scalable streaming-array for power-efficient stencil computation. SIGARCH Comput. Archit. News 39(4): 44-49 (2011) - [c16]Kentaro Sano, Yoshiaki Hatsuda, Satoru Yamamoto:
Scalable Streaming-Array of Simple Soft-Processors for Stencil Computations with Constant Memory-Bandwidth. FCCM 2011: 234-241 - [c15]Kentaro Sano:
SW and HW co-design of Connect6 accelerator with scalable streaming cores. FPT 2011: 1-4 - 2010
- [j5]Kentaro Sano, Luzhou Wang, Satoru Yamamoto:
Prototype implementation of array-processor extensible over multiple FPGAs for scalable stencil computation. SIGARCH Comput. Archit. News 38(4): 80-86 (2010) - [j4]Kentaro Sano, Luzhou Wang, Yoshiaki Hatsuda, Takanori Iizuka, Satoru Yamamoto:
FPGA-Array with Bandwidth-Reduction Mechanism for Scalable and Power-Efficient Numerical Simulations Based on Finite Difference Methods. ACM Trans. Reconfigurable Technol. Syst. 3(4): 21:1-21:35 (2010) - [c14]Kazuya Katahira, Kentaro Sano, Satoru Yamamoto:
FPGA-based lossless compressors of floating-point data streams to enhance memory bandwidth. ASAP 2010: 246-253 - [c13]Kentaro Sano, Kazuya Katahira, Satoru Yamamoto:
Segment-Parallel Predictor for FPGA-Based Hardware Compressor and Decompressor of Floating-Point Data Streams to Enhance Memory I/O Bandwidth. DCC 2010: 416-425 - [c12]Luzhou Wang, Kentaro Sano, Satoru Yamamoto:
Local-and-global stall mechanism for systolic computational-memory array on extensible multi-FPGA system. FPT 2010: 102-109
2000 – 2009
- 2008
- [c11]Kentaro Sano, Takeshi Nishikawa, Takayuki Aoki, Satoru Yamamoto:
Evaluating power and energy consumption of FPGA-based custom computing machines for scientific floating-point computation. FPT 2008: 301-304 - [c10]Kentaro Sano, Luzhou Wang, Yoshiaki Hatsuda, Satoru Yamamoto:
Scalable FPGA-array for high-performance and power-efficient computation based on difference schemes. HPRCTA@SC 2008: 1-9 - 2007
- [c9]Kentaro Sano, Takanori Iizuka, Satoru Yamamoto:
Systolic Architecture for Computational Fluid Dynamics on FPGAs. FCCM 2007: 107-116 - [c8]Kentaro Sano, Oliver Pell, Wayne Luk, Satoru Yamamoto:
FPGA-based Streaming Computation for Lattice Boltzmann Method. FPT 2007: 233-236 - 2005
- [j3]Takeshi Miura, Kentaro Sano, Ken-ichi Suzuki, Tadao Nakamura:
A Competitive Learning Algorithm with Controlling Maximum Distortion. J. Adv. Comput. Intell. Intell. Informatics 9(2): 166-174 (2005) - 2004
- [j2]Kentaro Sano, Yusuke Kobayashi, Tadao Nakamura:
Differential coding scheme for efficient parallel image composition on a PC cluster system. Parallel Comput. 30(2): 285-299 (2004) - [j1]Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa, Hiroaki Kobayashi, Tadao Nakamura:
Efficient parallel processing of competitive learning algorithms. Parallel Comput. 30(12): 1361-1383 (2004) - [c7]Shintaro Momose, Kentaro Sano, K. Suzuki, Tadao Nakamura:
Parallel competitive learning algorithm for fast codebook design on partitioned space. CLUSTER 2004: 449-457 - [c6]Kentaro Sano, Chiaki Takagi, Ryusuke Egawa, Ken-ichi Suzuki, Tadao Nakamura:
A Systolic Memory Architecture for Fast Codebook Design based on MMPDCL Algorithm. ITCC (1) 2004: 572-578 - 2003
- [c5]Hiroyuki Takizawa, Taira Nakajima, Kentaro Sano, Hiroaki Kobayashi:
A Comparison Study of Vector Quantization Codebook Design Algorithms based on the Equidistortion Principle. Applied Informatics 2003: 255-261 - 2002
- [c4]Kentaro Sano, Shintaro Momose, Hiroyuki Takizawa, Taira Nakajima, C. D. Lima, Hiroaki Kobayashi, Tadao Nakamura:
Parallel Algorithm for the Law-of-the-Jungle Learning to the Fast Design of Optimal Codebooks. IASTED PDCS 2002: 578-582 - [c3]C. D. Lima, Kentaro Sano, Tadao Nakamura:
Hardware Support for Concurrent Execution of Loops Containing Loop-carried Data Dependences. IASTED PDCS 2002: 718-723 - 2001
- [c2]Hiroaki Kobayashi, Ken-ichi Suzuki, Kentaro Sano, Yoshiyuki Kaeriyama, Yasumasa Saida, Nobuyuki Oba, Tadao Nakamura:
3DCGiRAM: An Intelligent Memory Architecture for Photo-Realistic Image Synthesis. ICCD 2001: 462-467
1990 – 1999
- 1997
- [c1]Kentaro Sano, Hiroyuki Kitajima, Hiroaki Kobayashi, Tadao Nakamura:
Parallel processing of the shear-warp factorization with the binary-swap method on a distributed-memory multiprocessor system. PRS 1997: 87-94
Coauthor Index
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