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Nam Ho

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2020 – today

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2024
[c15]
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  - conf/arcs/ZaourarBMFPHSPMSFDP24
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Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Carlos Falquez, Antoni Portero, Nam Ho, Estela Suarez, Polydoros Petrakis, Manolis Marazakis, Francesco Sgherzi, Ivan Fernandez, Romain Dolbeau, Dirk Pleiter:
Case Studies on the Impact and Challenges of Heterogeneous NUMA Architectures for HPC. ARCS 2024: 251-265
[c14]
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Fabian Schätzle, Carlos Falquez, Stefan Heinen, Nam Ho, Antoni Portero, Estela Suarez, Johannes Van Den Boom, Stefan van Waasen:
Modeling methodology for multi-die chip design based on gem5/SystemC co-simulation. RAPIDO@HiPEAC 2024: 35-41
2023
[c13]
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  - conf/arcs/PorteroFHPNMDCAPS23
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Antoni Portero, Carlos Falquez, Nam Ho, Polydoros Petrakis, Stepan Nassyr, Manolis Marazakis, Romain Dolbeau, Jorge Alejandro Nocua Cifuentes, Luis Bertran Alvarez, Dirk Pleiter, Estela Suarez:
COMPESCE: A Co-design Approach for Memory Subsystem Performance Analysis in HPC Many-Cores. ARCS 2023: 105-119
2021
[c12]
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  - conf/date/ArmejachBCD0HLL21
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Adrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji:
Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors. DATE 2021: 136-141
[c11]
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Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau:
Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS 2021: 18-29
2020
[j1]
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  - journals/ijhis/HoKP20
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Nam Ho, Paul Kaufmann, Marco Platzner:
Evolution of application-specific cache mappings. Int. J. Hybrid Intell. Syst. 16(3): 149-161 (2020)

2010 – 2019

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2019
[c10]
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  - conf/socpar/HoKP19
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Nam Ho, Paul Kaufmann, Marco Platzner:
Optimization of Application-Specific L1 Cache Translation Functions of the LEON3 Processor. SoCPaR 2019: 266-276
2018
[b1]
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Nam Ho:
FPGA-based reconfigurable cache mapping schemes: design and optimization. University of Paderborn, Germany, 2018
2017
[c9]
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  - conf/ahs/KaufmannHP17
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Paul Kaufmann, Nam Ho, Marco Platzner:
Evaluation methodology for complex non-deterministic functions: A case study in metaheuristic optimization of caches. AHS 2017: 206-213
[c8]
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Nam Ho, Ishraq Ibne Ashraf, Paul Kaufmann, Marco Platzner:
Accurate private/shared classification of memory accesses: A run-time analysis system for the LEON3 multi-core processor. DATE 2017: 788-793
[c7]
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Nam Ho, Paul Kaufmann, Marco Platzner:
Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. FPT 2017: 215-218
2015
[c6]
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Nam Ho, Abdullah Fathi Ahmed, Paul Kaufmann, Marco Platzner:
Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. AHS 2015: 1-7
[c5]
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  - conf/cf/HoMSSPG15
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Nam Ho, Andrea Mondelli, Alberto Scionti, Marco Solinas, Antoni Portero, Roberto Giorgi:
Enhancing an x86_64 multi-core architecture with data-flow execution support. Conf. Computing Frontiers 2015: 41:1-41:2
[c4]
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Andrea Mondelli, Nam Ho, Alberto Scionti, Marco Solinas, Antoni Portero, Roberto Giorgi:
Dataflow Support in x86_64 Multicore Architectures through Small Hardware Extensions. DSD 2015: 526-529
2014
[c3]
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  - conf/fpl/HoKP14
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Nam Ho, Paul Kaufmann, Marco Platzner:
A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. FPL 2014: 1-4
[c2]
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Nam Ho, Paul Kaufmann, Marco Platzner:
Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. ICES 2014: 31-37
2010
[c1]
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  - conf/soict/HoD10
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Nam Ho, Anh-Vu Dinh-Duc:
MemMON: run-time off-chip detection for memory access violation in embedded systems. SoICT 2010: 114-121

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