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ORCIDRafael Rodríguez-Sánchez 0001
Person information
- affiliation: Universidad Complutense de Madrid, Madrid, Spain
Other persons with the same name
- Rafael Rodríguez-Sánchez 0002 — Brown University, Providence, RI, USA
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2020 – today
- 2024
[j25]Rafael Rodríguez-Sánchez
, Adrián Castelló, Sandra Catalán, Francisco D. Igual, Enrique S. Quintana-Ortí:
Experiences with nested parallelism in task-parallel applications using malleable BLAS on multicore processors. Int. J. High Perform. Comput. Appl. 38(2): 55-68 (2024)- [c20]Héctor Martínez, Francisco D. Igual, Rafael Rodríguez-Sánchez, Sandra Catalán, Adrián Castelló, Enrique S. Quintana-Ortí:
Inference with Transformer Encoders on ARM and RISC-V Multicore Processors. Euro-Par (2) 2024: 377-392 - 2023
- [j24]Sandra Catalán, José R. Herrero, Francisco D. Igual, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez:
Fine-grain task-parallel algorithms for matrix factorizations and inversion on many-threaded CPUs. Concurr. Comput. Pract. Exp. 35(27) (2023) - [j23]Sandra Catalán, Francisco D. Igual, José R. Herrero, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Programming parallel dense matrix factorizations and inversion for new-generation NUMA architectures. J. Parallel Distributed Comput. 175: 51-65 (2023) - [i8]Héctor Martínez, Sandra Catalán, Francisco D. Igual, José R. Herrero, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Co-Design of the Dense Linear AlgebravSoftware Stack for Multicore Processors. CoRR abs/2304.14480 (2023) - 2022
- [c19]Sandra Catalán, Francisco D. Igual, Rafael Rodríguez-Sánchez, José R. Herrero, Enrique S. Quintana-Ortí:
NUMA-Aware Dense Matrix Factorizations and Inversion with Look-Ahead on Multicore Processors. SBAC-PAD 2022: 91-99 - [c18]Adrián Castelló, Sandra Catalán, Francisco D. Igual, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez:
QR Factorization Using Malleable BLAS on Multicore Processors. ISC Workshops 2022: 176-189 - 2021
- [j22]Pablo San Juan, Rafael Rodríguez-Sánchez, Francisco D. Igual, Pedro Alonso-Jordá, Enrique S. Quintana-Ortí:
Low precision matrix multiplication for efficient deep learning in NVIDIA Carmel processors. J. Supercomput. 77(10): 11257-11269 (2021) - [c17]Sandra Catalán, Francisco D. Igual, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Scalable Hybrid Loop- and Task-Parallel Matrix Inversion for Multicore Processors. IPDPS Workshops 2021: 679-687 - [c16]Sandra Catalán, Francisco D. Igual, Rafael Rodríguez-Sánchez, José R. Herrero, Enrique S. Quintana-Ortí:
A New Generation of Task-Parallel Algorithms for Matrix Inversion in Many-Threaded CPUs. PMAM@PPoPP 2021: 1-10 - 2020
- [j21]Sandra Catalán, Adrián Castelló, Francisco D. Igual, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Programming parallel dense matrix factorizations with look-ahead and OpenMP. Clust. Comput. 23(1): 359-375 (2020) - [j20]Rafael Rodríguez-Sánchez, Francisco D. Igual, Enrique S. Quintana-Ortí:
Integration and exploitation of intra-routine malleability in BLIS. J. Supercomput. 76(4): 2860-2875 (2020)
2010 – 2019
- 2019
- [j19]Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez, Robert A. van de Geijn:
A Case for Malleable Thread-Level Linear Algebra Libraries: The LU Factorization With Partial Pivoting. IEEE Access 7: 17617-17633 (2019) - [j18]Rafael Rodríguez-Sánchez, Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Andrés E. Tomás:
Look-ahead in the two-sided reduction to compact band forms for symmetric eigenvalue problems and the SVD. Numer. Algorithms 80(2): 635-660 (2019) - [j17]Andrés E. Tomás, Rafael Rodríguez-Sánchez, Sandra Catalán, Rocío Carratalá-Sáez, Enrique S. Quintana-Ortí:
Dynamic look-ahead in the reduction to band form for the singular value decomposition. Parallel Comput. 81: 22-31 (2019) - 2018
- [j16]Sandra Catalán, José R. Herrero, Francisco D. Igual, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí, Chris Adeniyi-Jones:
Multi-threaded dense linear algebra libraries for low-power asymmetric multicore processors. J. Comput. Sci. 25: 140-151 (2018) - [j15]Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez:
Energy balance between voltage-frequency scaling and resilience for linear algebra routines on low-power multicore architectures. Parallel Comput. 73: 28-39 (2018) - [j14]Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez:
Static scheduling of the LU factorization with look-ahead on asymmetric multicore processors. Parallel Comput. 76: 18-27 (2018) - [j13]Pedro Alonso, Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez:
Two-sided orthogonal reductions to condensed forms on asymmetric multicore processors. Parallel Comput. 78: 85-100 (2018) - [c15]Andrés E. Tomás, Rafael Rodríguez-Sánchez, Sandra Catalán, Enrique S. Quintana-Ortí:
Reduction to Band Form for the Singular Value Decomposition on Graphics Accelerators. PMAM@PPoPP 2018: 51-60 - [i7]Sandra Catalán, Adrián Castelló, Francisco D. Igual, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Programming Parallel Dense Matrix Factorizations with Look-Ahead and OpenMP. CoRR abs/1804.07017 (2018) - 2017
- [j12]Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Architecture-aware optimization of an HEVC decoder on asymmetric multicore processors. J. Real Time Image Process. 13(1): 25-38 (2017) - [j11]Luis Costero, Francisco D. Igual, Katzalin Olcoz, Sandra Catalán, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Revisiting conventional task schedulers to exploit asymmetry in multi-core architectures for dense linear algebra operations. Parallel Comput. 68: 59-76 (2017) - [j10]Sandra Catalán, Francisco D. Igual, Rafael Mayo, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Time and energy modeling of a high-performance multi-threaded Cholesky factorization. J. Supercomput. 73(1): 139-151 (2017) - [c14]Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Tiles-and WPP-based HEVC Decoding on Asymmetric Multi-core Processors. BigMM 2017: 299-302 - [c13]Sandra Catalán, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí, José R. Herrero:
Static Versus Dynamic Task Scheduling of the Lu Factorization on ARM big. LITTLE Architectures. IPDPS Workshops 2017: 733-742 - [c12]Pedro Alonso, Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez:
Reduction to Tridiagonal Form for Symmetric Eigenproblems on Asymmetric Multicore Processors. PMAM@PPoPP 2017: 39-47 - [i6]Rafael Rodríguez-Sánchez, Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Andrés E. Tomás:
Two-Sided Reduction to Compact Band Forms with Look-Ahead. CoRR abs/1709.00302 (2017) - 2016
- [j9]Sandra Catalán, Francisco D. Igual, Rafael Mayo, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Architecture-aware configuration and scheduling of matrix multiplication on asymmetric multicore processors. Clust. Comput. 19(3): 1037-1051 (2016) - [c11]Luis Costero, Francisco D. Igual, Katzalin Olcoz, Sandra Catalán, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Refactoring Conventional Task Schedulers to Exploit Asymmetric ARM big.LITTLE Architectures in Dense Linear Algebra. IPDPS Workshops 2016: 692-701 - [i5]Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Architecture-Aware Optimization of an HEVC decoder on Asymmetric Multicore Processors. CoRR abs/1601.05313 (2016) - [i4]Sandra Catalán, José R. Herrero, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez, Robert A. van de Geijn:
A Case for Malleable Thread-Level Linear Algebra Libraries: The LU Factorization with Partial Pivoting. CoRR abs/1611.06365 (2016) - 2015
- [j8]Pedro Alonso, Sandra Catalán, Francisco D. Igual, Rafael Mayo, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Time and energy modeling of high-performance Level-3 BLAS on x86 architectures. Simul. Model. Pract. Theory 55: 77-94 (2015) - [j7]Enrique de la Torre, Rafael Rodríguez-Sánchez, José Luis Martínez:
Fast video transcoding from HEVC to VP9. IEEE Trans. Consumer Electron. 61(3): 336-343 (2015) - [j6]Alberto Corrales-García, Rafael Rodríguez-Sánchez, José Luis Martínez, Gerardo Fernández-Escribano, Francisco J. Quiles:
Multimedia Communications Using a Fast and Flexible DVC to H.264/AVC/SVC Transcoder. J. Signal Process. Syst. 79(3): 211-232 (2015) - [c10]Rafael Rodríguez-Sánchez, Maria Teresa Alonso, José Luis Martínez, Rafael Mayo, Enrique S. Quintana-Ortí:
Time and energy modeling of an INTRA-ONLY HEVC encoder. VCIP 2015: 1-4 - [c9]Enrique de la Torre, Rafael Rodríguez-Sánchez, José Luis Martínez:
HEVC to VP9 transcoder. VCIP 2015: 1-4 - [i3]Sandra Catalán, Francisco D. Igual, Rafael Mayo, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Architecture-Aware Configuration and Scheduling of Matrix Multiplication on Asymmetric Multicore Processors. CoRR abs/1506.08988 (2015) - [i2]Sandra Catalán, Francisco D. Igual, Rafael Mayo, Luis Piñuel, Enrique S. Quintana-Ortí, Rafael Rodríguez-Sánchez:
Performance and Energy Optimization of Matrix Multiplication on Asymmetric big.LITTLE Processors. CoRR abs/1507.05129 (2015) - [i1]Sandra Catalán, José R. Herrero, Francisco D. Igual, Rafael Rodríguez-Sánchez, Enrique S. Quintana-Ortí:
Multi-Threaded Dense Linear Algebra Libraries for Low-Power Asymmetric Multicore Processors. CoRR abs/1511.02171 (2015) - 2014
- [c8]Rafael Rodríguez-Sánchez, Francisco D. Igual, José Luis Martínez, Rafael Mayo, Enrique S. Quintana-Ortí:
Parallel performance and energy efficiency of modern video encoders on multithreaded architectures. EUSIPCO 2014: 191-195 - [c7]Álvaro García, Rafael Rodríguez-Sánchez, José Luis Martínez:
An smpUMHexagonS-based motion estimation algorithm for heterogeneous architectures. ICIP 2014: 1243-1247 - 2013
- [j5]Rafael Rodríguez-Sánchez, José Luis Martínez, Jan De Cock, Gerardo Fernández-Escribano, Bart Pieters, José L. Sánchez, José M. Claver, Rik Van de Walle:
3D high definition video coding on a GPU-based heterogeneous system. Comput. Electr. Eng. 39(8): 2623-2637 (2013) - [j4]Rafael Rodríguez-Sánchez, José Luis Martínez, Jan De Cock, Gerardo Fernández-Escribano, Bart Pieters, José L. Sánchez, José Manuel Claver, Rik Van de Walle:
Adapting hierarchical bidirectional inter prediction on a GPU-based platform for 2D and 3D H.264 video coding. EURASIP J. Adv. Signal Process. 2013: 67 (2013) - [j3]Rafael Rodríguez-Sánchez, José Luis Martínez, Gerardo Fernández-Escribano, José Luis Sánchez Garcia, José Manuel Claver:
H.264/AVC inter prediction on accelerator-based multi-core systems. Multim. Tools Appl. 66(3): 361-381 (2013) - [j2]Rafael Rodríguez-Sánchez, José Luis Martínez, Gerardo Fernández-Escribano, José Manuel Claver, José L. Sánchez:
H.264/AVC inter prediction for heterogeneous computing systems. J. Supercomput. 64(1): 79-88 (2013) - [c6]Luong Pham Van, Jan De Cock, Glenn Van Wallendael, Sebastiaan Van Leuven, Rafael Rodríguez-Sánchez, José Luis Martínez, Peter Lambert, Rik Van de Walle:
Fast transrating for high efficiency video coding based on machine learning. ICIP 2013: 1573-1577 - [c5]Rafael Rodríguez-Sánchez, José Luis Martínez, Jan De Cock, José L. Sánchez, José M. Claver, Rik Van de Walle:
Low delay H.264/AVC bidirectional inter prediction on a GPU. ICIP 2013: 2111-2115 - 2012
- [j1]Rafael Rodríguez-Sánchez, José Luis Martínez, Gerardo Fernández-Escribano, José L. Sánchez, José M. Claver, Pedro Diaz:
Optimizing H.264/AVC interprediction on a GPU-based framework. Concurr. Comput. Pract. Exp. 24(14): 1607-1624 (2012) - [c4]Rafael Rodríguez-Sánchez, José Luis Martínez, Gerardo Fernández-Escribano, José Luis Sánchez Garcia, José Manuel Claver:
A Fast GPU-Based Motion Estimation Algorithm for HD 3D Video Coding. ISPA 2012: 166-173 - [c3]Rafael Rodríguez-Sánchez, José Luis Martínez, Gerardo Fernández-Escribano, José Luis Sánchez Garcia, José Manuel Claver:
A Fast GPU-Based Motion Estimation Algorithm for H.264/AVC. MMM 2012: 551-562 - 2011
- [c2]Rafael Rodríguez-Sánchez, José Luis Martínez, Gerardo Fernández-Escribano, José M. Claver, José L. Sánchez:
Reducing complexity in H.264/AVC motion estimation by using a GPU. MMSP 2011: 1-6 - 2010
- [c1]Alberto Corrales-García, Rafael Rodríguez-Sánchez, José Luis Martínez, Gerardo Fernández-Escribano, José M. Claver, José Luis Sánchez Garcia:
A GPU-Based DVC to H.264/AVC Transcoder. HAIS (2) 2010: 233-240
Coauthor Index
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