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ORCIDTatsuo Higuchi 0001
Person information
- affiliation: Tohoku University
Other persons with the same name
- Tatsuo Higuchi 0002 — Hitachi
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2010 – 2019
- 2010
[j63]Koichi Ito
, Ayumi Morita, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi:
Score-Level Fusion of Phase-Based and Feature-Based Fingerprint Matching Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(3): 607-616 (2010)
2000 – 2009
- 2009
- [j62]Masahiko Hiratsuka, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi:
Toward Biomolecular Computers Using Reaction-Diffusion Dynamics. Int. J. Nanotechnol. Mol. Comput. 1(3): 17-25 (2009) - [j61]Naofumi Homma, Yuki Watanabe, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Systematic Approach to Designing Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. J. Multiple Valued Log. Soft Comput. 15(4): 329-340 (2009) - 2008
- [j60]Koichi Ito, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi:
A Palmprint Recognition Algorithm Using Phase-Only Correlation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(4): 1023-1030 (2008) - [j59]Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Arithmetic Circuit Verification Based on Symbolic Computer Algebra. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(10): 3038-3046 (2008) - [j58]Masahiko Hiratsuka, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi:
Shortest Path Search Using a Reaction-Diffusion Processor. Int. J. Unconv. Comput. 4(2): 113-124 (2008) - [j57]Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams. IEEE Trans. Computers 57(12): 1633-1646 (2008) - [c77]Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Arithmetic module generator with algorithm optimization capability. ISCAS 2008: 1796-1799 - [c76]Yuki Watanabe, Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
High-Level Design of Multiple-Valued Arithmetic Circuits Based on Arithmetic Description Language. ISMVL 2008: 112-117 - 2007
- [j56]Masanori Natsui, Yoshiaki Tadokoro, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Synthesis of current mirrors based on evolutionary graph generation with transmigration capability. IEICE Electron. Express 4(3): 88-93 (2007) - [j55]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
Design of a Two-Bit-Per-Cell Content-Addressable Memory Using Single-Electron Transistors. J. Multiple Valued Log. Soft Comput. 13(3): 249-266 (2007) - [j54]Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Design of Multiple-valued Arithmetic Circuits Using Counter Tree Diagrams. J. Multiple Valued Log. Soft Comput. 13(4-6): 487-502 (2007) - [c75]Yuki Watanabe, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Application of symbolic computer algebra to arithmetic circuit verification. ICCD 2007: 25-32 - [c74]Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams. ISMVL 2007: 31 - 2006
- [j53]Koichi Ito, Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi:
A Shortest Path Search Algorithm Using an Excitable Digital Reaction-Diffusion System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(3): 735-743 (2006) - [j52]Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Systematic Interpretation of Redundant Arithmetic Adders in Binary and Multiple-Valued Logic. IEICE Trans. Electron. 89-C(11): 1645-1654 (2006) - [j51]Naofumi Homma, Yuki Watanabe, Takafumi Aoki, Tatsuo Higuchi:
Formal Design of Arithmetic Circuits Based on Arithmetic Description Language. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3500-3509 (2006) - [c73]Koichi Ito, Ayumi Morita, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi:
A Fingerprint Recognition Algorithm Combining Phase-Based Image Matching and Feature-Based Matching. ICB 2006: 316-325 - [c72]Hiroshi Nakajima, Koji Kobayashi, Makoto Morikawa, Atsushi Katsumata, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi:
Fast and Robust Fingerprint Identification Algorithm and Its Application to Residential Access Controller. ICB 2006: 326-333 - [c71]Koichi Ito, Takafumi Aoki, Hiroshi Nakajima, Koji Kobayashi, Tatsuo Higuchi:
A Palmprint Recognition Algorithm using Phase-Based Image Matching. ICIP 2006: 2669-2672 - [c70]Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Algorithm-level interpretation of fast adder structures in binary and multiple-valued logic. ISMVL 2006: 2 - [c69]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Katsuhiko Nishiguchi, Yasuo Takahashi:
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2006: 19 - 2005
- [j50]Yoshifumi Sasaki, Koichi Ito, Takafumi Aoki, Tatsuo Higuchi:
A compact cluster computer with embedded CPUs and its application to rapid prototyping of fingerprint verification system. IEICE Electron. Express 2(17): 465-470 (2005) - [j49]Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Design of Multiple-Valued Logic Circuits Using Graph-Based Evolutionary Synthesis. J. Multiple Valued Log. Soft Comput. 11(5-6): 519-544 (2005) - [j48]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Prototype Fabrication of Field-Programmable Digital Filter LSIs Using Multiple-Valued Current-Mode Logic - Device Scaling and Future Prospects. J. Multiple Valued Log. Soft Comput. 11(5-6): 545-565 (2005) - [c68]Koichi Ito, Ayumi Morita, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Nakajima, Koji Kobayashi:
A fingerprint recognition algorithm using phase-based image matching for low-quality fingerprints. ICIP (2) 2005: 33-36 - [c67]Katsuhiko Degawa, Takafumi Aoki, Hiroshi Inokawa, Tatsuo Higuchi, Yasuo Takahashi:
A Two-Bit-per-Cell Content-Addressable Memory Using Single-Electron Transistors. ISMVL 2005: 32-38 - 2004
- [c66]Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Multiplier Block Synthesis Using Evolutionary Graph Generation. Evolvable Hardware 2004: 79-82 - [c65]Naofumi Homma, Jun Sakiyama, Taihei Wakamatsu, Takafumi Aoki, Tatsuo Higuchi:
A systematic approach for analyzing fast addition algorithms using counter tree diagrams. ISCAS (5) 2004: 197-200 - [c64]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi, Hiroshi Inokawa, Yasuo Takahashi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part I: Basic Components for Binary, Multiple-Valued and Mixed-Mode Logic. ISMVL 2004: 262-268 - [c63]Hiroshi Inokawa, Yasuo Takahashi, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
A Single-Electron-Transistor Logic Gate Family and Its Application - Part II: Design and Simulation of a 7-3 Parallel Counter with Linear Summation and Multiple-Valued Latch Functions. ISMVL 2004: 269-274 - [c62]Kazuya Ishida, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Design and Verification of Parallel Multipliers Using Arithmetic Description Language: ARITH. ISMVL 2004: 334-339 - [c61]Masanori Natsui, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Topology-Oriented Design of Analog Circuits Based on Evolutionary Graph Generation. PPSN 2004: 342-351 - 2003
- [j47]Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi:
Evolutionary Synthesis of Arithmetic Circuit Structures. Artif. Intell. Rev. 20(3-4): 199-232 (2003) - [j46]Koichi Ito, Takafumi Aoki, Tatsuo Higuchi:
Fingerprint Restoration Using Digital Reaction-Diffusion System and Its Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(8): 1916-1924 (2003) - [j45]Kenji Takita, Takafumi Aoki, Yoshifumi Sasaki, Tatsuo Higuchi, Koji Kobayashi:
High-Accuracy Subpixel Image Registration Based on Phase-Only Correlation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(8): 1925-1934 (2003) - [j44]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
Design of a Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(8): 2001-2010 (2003) - [j43]Jun Sakiyama, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Counter Tree Diagrams: A Unified Framework for Analyzing Fast Addition Algorithms. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3009-3019 (2003) - [j42]Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi:
Counter Tree Diagrams: A Unified Representation of Fast Addition Algorithms. J. Multiple Valued Log. Soft Comput. 9(1): 87-108 (2003) - [c60]Naofumi Homma, Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi:
VLSI circuit design using an object-oriented framework of evolutionary graph generation system. IEEE Congress on Evolutionary Computation 2003: 115-122 - [c59]Koichi Ito, Takafumi Aoki, Tatsuo Higuchi:
Design of a digital reaction-diffusion system for restoring blurred fingerprint images. ISCAS (4) 2003: 77-80 - [c58]Naofumi Homma, Takafumi Aoki, Makoto Motegi, Tatsuo Higuchi:
A framework of evolutionary graph generation system and its application to circuit synthesis. ISCAS (5) 2003: 201-204 - [c57]Jun Sakiyama, Takafumi Aoki, Tatsuo Higuchi:
Counter Tree Diagrams for Design and Analysis of Fast Addition Algorithms. ISMVL 2003: 91-98 - [c56]Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi:
A Field-Programmable Digital Filter Chip Using Multiple-Valued Current-Mode Logic. ISMVL 2003: 213-220 - 2002
- [j41]Dingjun Chen, Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi:
Parallel Evolutionary Design of Constant-Coefficient Multipliers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(2): 508-512 (2002) - [j40]Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi:
Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(9): 2061-2071 (2002) - [j39]Dingjun Chen, Takafumi Aoki, Naofumi Homma, Toshiki Terasaki, Tatsuo Higuchi:
Graph-based evolutionary design of arithmetic circuits. IEEE Trans. Evol. Comput. 6(1): 86-100 (2002) - [c55]Mochamad Hariadi, Akio Harada, Takafumi Aoki, Tatsuo Higuchi:
An LVQ-based technique for human motion segmentation. APCCAS (2) 2002: 171-176 - [c54]Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Graph-based individual representation for evolutionary synthesis of arithmetic circuits. IEEE Congress on Evolutionary Computation 2002: 1492-1497 - [c53]Mochamad Hariadi, Akio Harada, Takafumi Aoki, Tatsuo Higuchi:
Pixel-wise human motion segmentation using learning vector quantization. ICARCV 2002: 1439-1444 - [c52]Yasushi Yuminaka, Tatsuya Morishita, Takafumi Aoki, Tatsuo Higuchi:
Multiple-Valued Data Recovery Techniques for Band-Limited Channels in VLSI. ISMVL 2002: 54-60 - [c51]Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi:
Parallel Evolutionary Graph Synthesis on a PC Cluster and Its Application to Multiple-Valued Circuit Synthesis. ISMVL 2002: 96-103 - [c50]Makoto Motegi, Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Evolutionary Graph Generation System and Its Application to Bit-Serial Arithmetic Circuit Synthesis. PPSN 2002: 831-840 - 2001
- [c49]Dingjun Chen, Takafumi Aoki, Naofumi Homma, Tatsuo Higuchi:
Distributed evolutionary design of constant-coefficient multipliers. ICECS 2001: 249-252 - [c48]Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi:
Evolutionary graph generation system with transmigration capability for arithmetic circuit design. ISCAS (5) 2001: 171-174 - [c47]Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi:
A Model of Reaction-Diffusion Cellular Automata for Massively Parallel Molecular Computing. ISMVL 2001: 247-252 - [c46]Masanori Natsui, Takafumi Aoki, Tatsuo Higuchi:
Synthesis of Multiple-Valued Arithmetic Circuits Using Evolutionary Graph Generation. ISMVL 2001: 253-258 - 2000
- [c45]Takafumi Aoki, Kimihiko Nakazawa, Tatsuo Higuchi:
High-Radix Parallel VLSI Dividers without Using Quotient Digit Selection Tables. ISMVL 2000: 345-354 - [c44]Yasushi Yuminaka, Osamu Katoh, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi:
An Efficient Data Transmission Technique for VLSI Systems Based on Multiple-Valued Code-Division Multiple Access. ISMVL 2000: 430-437
1990 – 1999
- 1999
- [c43]Takafumi Aoki, Ken-ichi Hoshi, Tatsuo Higuchi:
Redundant Complex Arithmetic and Its Application to Complex Multiplier Design. ISMVL 1999: 200-207 - 1998
- [c42]Takafumi Aoki, Tatsuo Higuchi:
Set-Valued Logic Circuits for Next Generation VLSI Architectures. ISMVL 1998: 140-147 - [c41]Yasushi Yuminaka, Yoshisat Sasaki, Takafumi Aoki, Tatsuo Higuchi:
Wave-Parallel Computing Systems using Multiple-Valued Pseudo-Orthogonal Sequences. ISMVL 1998: 148-154 - 1997
- [j38]Koji Kobayashi, Michitaka Kameyama, Tatsuo Higuchi:
Communication network protocol for real-time distributed control and its LSI implementation. IEEE Trans. Ind. Electron. 44(3): 418-426 (1997) - [c40]Takafumi Aoki, Hiroaki Amada, Tatsuo Higuchi:
Real/Complex Reconfigurable Arithmetic Using Redundant Complex Number Systems. IEEE Symposium on Computer Arithmetic 1997: 200-207 - [c39]Masahiko Hiratsuka, Takafumi Aoki, Tatsuo Higuchi:
Enzyme Transistor Circuits for Biomolecular Computing. ISMVL 1997: 47-54 - 1996
- [j37]Qiangfu Zhao, Tatsuo Higuchi:
Efficient learning of NN-MLP based on individual evolutionary algorithm. Neurocomputing 13(2-4): 201-215 (1996) - [j36]Qiangfu Zhao, Tatsuo Higuchi:
Minimization of nearest neighbor classifiers based on individual evolutionary algorithm. Pattern Recognit. Lett. 17(2): 125-131 (1996) - [j35]Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi:
Author's Reply. IEEE Trans. Computers 45(5): 639 (1996) - [j34]Qiangfu Zhao, Tatsuo Higuchi:
Evolutionary learning of nearest-neighbor MLP. IEEE Trans. Neural Networks 7(3): 762-767 (1996) - [c38]Young-Ho Lee, Masayuki Kawamata, Tatsuo Higuchi:
GA-based design of multiplierless 2-D state-space digital filters with very small roundoff noise. ICASSP 1996: 1283-1286 - [c37]Yasushi Yuminaka, Yoshisato Sasaki, Takafumi Aoki, Tatsuo Higuchi:
Wave-Parallel Computing Technique for Neural Networks Based on Amplitude-Modulated Waves. ISMVL 1996: 210-215 - 1995
- [c36]Qiangfu Zhao, Tatsuo Higuchi:
An Evolutionary Algorithm for Solving Multi-Individual-Multi-Task Problems. BIES 1995: 61-68 - [c35]Shinichi Shionoya, Takafumi Aoki, Tatsuo Higuchi:
Multiwave Interconnection Networks for MCM-based Parallel Processing. Euro-Par 1995: 593-607 - [c34]Young-Ho Lee, Masayuki Kawamata, Tatsuo Higuchi:
Design of 2-D state-space digital filters with powers-of-two coefficients based on a genetic algorithm. ICIP 1995: 133-136 - [c33]S. Sakurai, Takafumi Aoki, Tatsuo Higuchi:
Wire-Free Computing Circuits Using Optical Wave-Casting. ISMVL 1995: 8-13 - [c32]Yuji Ohi, Takafumi Aoki, Tatsuo Higuchi:
Redundant Complex Number Systems. ISMVL 1995: 14-19 - [c31]Qiangfu Zhao, Tatsuo Higuchi:
Individual Evolutionary Algorithm and its Application to Learning of Nearest Neighbor Based MLP. IWANN 1995: 396-403 - 1994
- [j33]Yoshichika Fujioka, Michitaka Kameyama, Tatsuo Higuchi:
Coordinate Transformation VLSI Processor for Redundant Manipulator Control. J. Robotics Mechatronics 6(2): 124-130 (1994) - [j32]Shigeki Abe, Michitaka Kameyama, Tatsuo Higuchi:
Design of an Intelligent Fault-Tolerant System for Real-World Applications. J. Robotics Mechatronics 6(2): 150-154 (1994) - [j31]Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi:
High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits. IEEE Trans. Computers 43(1): 34-42 (1994) - [c30]Masayuki Kawamata, Masaki Nagahisa, Tatsuo Higuchi:
Multi-resolution Tree Search for Iterated Transformation Theory-Based Coding. ICIP (3) 1994: 137-141 - [c29]Masayuki Kawamata, Jun Imakubo, Tatsuo Higuchi:
Optimal Design Method of 2-D IIR Digital Filters Based on a Simple Genetic Algorithm. ICIP (1) 1994: 780-784 - [c28]Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi:
Design of Wave-Parallel Computing Circuits for Densely Connected Architectures. ISMVL 1994: 207-214 - [c27]Yukio Watanabe, Takafumi Aoki, Tatsuo Higuchi:
Design of Multiwave Computing Circuits Based on a Modle of Integrated Opto-Electronic Devices. ISMVL 1994: 215-222 - [c26]Takashi Takimoto, Takafumi Aoki, Tatsuo Higuchi:
Design of Multiplex Interconnection Networks for Massively Parallel Computing Systems. ISMVL 1994: 231-238 - 1993
- [j30]Tian-Bo Deng, Masayuki Kawamata, Tatsuo Higuchi:
Design of 2-d Digital filters Based on the Optimal Decomposition of Magnitude Specifications. J. Circuits Syst. Comput. 3(3): 733-756 (1993) - [j29]Shoui Kaqahito, Makoto Ishida, Tetsuro Nakamura, Kentaro Mizuno, Michitaka Kameyama, Tatsuo Higuchi:
Multi-valued current-mode parallel multiplier based on redundant positive-digit number representations. Syst. Comput. Jpn. 24(5): 40-52 (1993) - [c25]Masayuki Kawamata, Eiichiro Kawakami, Tatsuo Higuchi:
Realization of lattice-form separable-denominator 2D adaptive filters. ISCAS 1993: 295-298 - [c24]Yasushi Iwata, Masayuki Kawamata, Tatsuo Higuchi:
Design of Fine Grain VLSI Array Processor for Real-time 2-D Digital Filtering. ISCAS 1993: 1559-1562 - [c23]Satoshi Aragaki, Takahiro Hanyu, Tatsuo Higuchi:
A Multiple-Valued Content-Addressable Memory Using Logic-Value Conversion and Threshold Functions. ISMVL 1993: 170-175 - [c22]Takafumi Aoki, Tatsuo Higuchi:
Impact of Interconnection-Free Biomolecular Computing. ISMVL 1993: 271-276 - [c21]Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi:
Design of Set-Valued Logic Networks for Wave-Parallel Computing. ISMVL 1993: 277-282 - 1992
- [j28]Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi:
Interconnection-Free Biomolecular Computing. Computer 25(11): 41-50 (1992) - [j27]Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi:
Design of an ultrahigher-valued biocomputing system based on set-valued logic networks. Syst. Comput. Jpn. 23(7): 35-44 (1992) - [c20]Takahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi:
Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based Systems. ISMVL 1992: 274-281 - [c19]Shuichi Maeda, Takafumi Aoki, Tatsuo Higuchi:
Set-Valued Logic Networks Based on Optical Wavelength Multiplexing. ISMVL 1992: 282-290 - [c18]Katsuhiko Shimabukuro, Michitaka Kameyama, Tatsuo Higuchi:
Design of a Multiple-Valued VLSI Processor for Digital Control. ISMVL 1992: 322-329 - [c17]Makoto Honda, Michitaka Kameyama, Tatsuo Higuchi:
Residue Arithmetic Based Multiple-Valued VLSI Image Processor. ISMVL 1992: 330-336 - [c16]Saneaki Tamaki, Michitaka Kameyama, Tatsuo Higuchi:
Code Assignment Algorithm for Highly Parallel Multiple-Valued Combinatorial Circuits. ISMVL 1992: 382-388 - 1991
- [j26]Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi:
Design of a robust fault-tolerant multiplier. Syst. Comput. Jpn. 22(2): 10-18 (1991) - [j25]Shugang Wei, Michitaka Kameyama, Tatsuo Higuchi:
Performance evaluation of a multivalued rsa encryption vlsi. Syst. Comput. Jpn. 22(7): 12-21 (1991) - [c15]Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi:
High-Performance VLSI Processor for Robot Inverse Dynamics Computation. ICCD 1991: 608-611 - [c14]Yasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi:
Design of a Set Logic Network Based on Frequency Multiplexing and Its Applications to Image Processing. ISMVL 1991: 8-15 - [c13]Takahiro Hanyu, Yasushi Kojima, Tatsuo Higuchi:
A Multiple-Valued Logic Artay VLSI Based on Two-Transistor Delta Literal Circuit and Its Application to Real-Time Reasoning Systems. ISMVL 1991: 16-23 - [c12]Takahiro Hanyu, Tatsuo Higuchi:
A Floating-Gate-MOS-Based Multiple-Valued Associative Memory. ISMVL 1991: 24-31 - [c11]Takafumi Aoki, Michitaka Kameyama, Tatsuo Higuchi:
Design of Interconnection-Free Biomolecular Computing System. ISMVL 1991: 173-180 - 1990
- [j24]Tatsuo Higuchi:
High-Performance LSI for Kinematics Computation. J. Robotics Mechatronics 2(2): 138 (1990) - [j23]Tadao Amada, Michitaka Kameyama, Tatsuo Higuchi:
Design of a Parallel Collision Detection Check VLSI Processor for Robot Manipulator. J. Robotics Mechatronics 2(6): 418-423 (1990) - [j22]Somchai Kittichaikoonkit, Michitaka Kameyama, Tatsuo Higuchi:
Design of a Matrix Multiply-Addition VLSI Processor for Robot control. J. Robotics Mechatronics 2(6): 424-430 (1990) - [j21]Tatsuo Higuchi, Michitaka Kameyama:
Robot Electronics System. J. Robotics Mechatronics 2(6): 471-473 (1990) - [j20]Michitaka Kameyama, Shugang Wei, Tatsuo Higuchi:
Design of an RSA Encryption Processor Based on Signed-Digit Multivalued Arithmetic Circuits. Syst. Comput. Jpn. 21(6): 21-31 (1990) - [j19]Takeshi Kasuga, Michitaka Kameyama, Tatsuo Higuchi:
Design of a fault-tolerant arithmetic circuit based on distributed coding and its evaluation. Syst. Comput. Jpn. 21(8): 59-71 (1990) - [j18]Michitaka Kameyama, Takafumi Aoki, Tatsuo Higuchi:
Design of a Highly Parallel Ultrahigher-Valued Logic Network Based on a Bio-Device Model. Syst. Comput. Jpn. 21(9): 1-12 (1990) - [c10]Takahiro Hanyu, Tatsuo Higuchi:
Design of a High-Density Multiple-Valued Content-Addressable Memory Based on Floating-Gate MOS Devices. ISMVL 1990: 18-23 - [c9]Michitaka Kameyama, Masahiro Nomura, Tatsuo Higuchi:
Modular Design of Multiple-Valued Arithmetic VLSI System Using Signed-Digit Number System. ISMVL 1990: 355-362
1980 – 1989
- 1989
- [j17]Michitaka Kameyama, Tatsuo Higuchi:
VLSI Computer for Robotics. J. Robotics Mechatronics 1(1): 68-73 (1989) - [j16]Takahiro Hanyu, Tatsuo Higuchi:
High-density quaternary logic array chip for knowledge information processing systems. IEEE J. Solid State Circuits 24(4): 916-921 (1989) - [j15]Michitaka Kameyama, Tsutomu Sekibe, Tatsuo Higuchi:
Highly parallel residue arithmetic chip based on multiple-valued bidirectional current-mode logic. IEEE J. Solid State Circuits 24(5): 1404-1411 (1989) - [j14]Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi:
Bi-directional current-mode basic circuits for the multilevel signed-digit arithmetic and their evaluation. Syst. Comput. Jpn. 20(6): 69-79 (1989) - [j13]Takahiro Hanyu, Tatsuo Higuchi:
Design of a Multiple-Valued Associative Memory. Syst. Comput. Jpn. 20(12): 23-33 (1989) - [c8]Michitaka Kameyama, Takao Matsumoto, Hideki Egami, Tatsuo Higuchi:
Implementation of a high performance LSI for inverse kinematics computation. ICRA 1989: 757-762 - 1988
- [j12]Michitaka Kameyama, Shoji Kawahito, Tatsuo Higuchi:
A Multiplier Chip with Multiple-Valued Bidirectional Current-Mode Logic Circuits. Computer 21(4): 43-56 (1988) - [j11]Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi, Haruyasu Yamada:
A 32*32-bit multiplier using multiple-valued MOS current-mode circuits. IEEE J. Solid State Circuits 23(1): 124-132 (1988) - [j10]Xi Yue Huang, Michitaka Kameyama, Tatsuo Higuchi:
Design of a time-optimal digital control system for a dc-servomotor with amplitude limitation. Syst. Comput. Jpn. 19(2): 64-73 (1988) - [j9]Michitaka Kameyama, Li Zheng, Tatsuo Higuchi:
Design of a Fault-Tolerant System Based on Knowledge-Engineering Approach and Its Application to a Digital Control System. Syst. Comput. Jpn. 19(12): 81-91 (1988) - 1987
- [j8]Takahiro Hanyu, Michitaka Kameyama, Tatsuo Higuchi:
Design and implementation of an nmos image processor based on quaternary logic. Syst. Comput. Jpn. 18(3): 92-106 (1987) - [j7]Shoji Kawahito, Michitaka Kameyama, Tatsuo Higuchi:
Design of VLSI-oriented radix-4 signed-digit arithmetic circuits using multiple-valued logic. Syst. Comput. Jpn. 18(4): 41-52 (1987) - [j6]Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi:
Design of micropower CMOS quaternary memory circuits. Syst. Comput. Jpn. 18(11): 61-69 (1987) - 1986
- [j5]Chotei Zukeran, Chushin Afuso, Michitaka Kameyama, Tatsuo Higuchi:
Design of low-power quaternary CMOS logic circuits. Syst. Comput. Jpn. 17(3): 93-101 (1986) - [j4]Nobuhiro Tomabechi, Michitaka Kameyama, Tatsuo Higuchi:
Design of lsi-oriented digital signal processing system Based on Pulse-Train Residue Arithmetic Circuits. Syst. Comput. Jpn. 17(6): 76-84 (1986) - [c7]Masami Iwatsuki, Masayuki Kawamata, Tatsuo Higuchi:
Synthesis of minimum sensitivity structures in linear systems using controllability and observability measures. ICASSP 1986: 501-504 - [c6]Tao Lin, Masayuki Kawamata, Tatsuo Higuchi:
A unified study on the roundoff noise in 2-D state space digital filters. ICASSP 1986: 1045-1048 - [c5]Qiangfu Zhao, Masayuki Kawamata, Tatsuo Higuchi:
A unified design method of state-space digital filters using system balancing concept. ICASSP 1986: 2579-2582 - 1985
- [j3]Masayuki Kawamata, Tatsuo Higuchi:
A unified approach to the optimal synthesis of fixed-point state-space digital filters. IEEE Trans. Acoust. Speech Signal Process. 33(4): 911-920 (1985) - 1981
- [c4]Yoshiaki Tadokoro, Tatsuo Higuchi:
Another discrete Fourier transform computation with small multiplications via the Walsh transform. ICASSP 1981: 306-309 - 1980
- [c3]Masayuki Kawamata, Tatsuo Higuchi:
A sufficient condition for absence of overflow oscillations in arbitrary digital filters based on the element equations. ICASSP 1980: 85-88
1970 – 1979
- 1979
- [c2]Tatsuo Higuchi, Hiroski Takeo:
A state-space approach for elimination of limit cycles in digital filters with arbitrary structures. ICASSP 1979: 355-358 - 1978
- [c1]Tatsuo Higuchi, Hisamitsu Hoshi:
Special-purpose ternary computer for digital filtering. MVL 1978: 47-54 - 1977
- [j2]Tatsuo Higuchi, Michitaka Kameyama:
Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters. IEEE Trans. Computers 26(12): 1212-1221 (1977) - [j1]Michitaka Kameyama, Tatsuo Higuchi:
Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module. IEEE Trans. Computers 26(12): 1297-1302 (1977)
Coauthor Index
[j63] [j62] [j61] [j60] [j59] [j58] [j57] [c77] [c76] [j56] [j55] [j54] [c75] [c74] [j53] [j52] [j51] [c73] [c72] [c71] [c70] [c69] [j50] [j49] [j48] [c68] [c67] [c66] [c65] [c64] [c63] [c62] [c61] [j47] [j46] [j45] [j44] [j43] [j42] [c60] [c59] [c58] [c57] [c56] [j41] [j40] [j39] [c55] [c54] [c53] [c52] [c51] [c50] [c49] [c48] [c47] [c46] [c45] [c44] [c43] [c42] [c41] [c40] [c39] [c37] [c35] [c33] [c32] [c28] [c27] [c26] [c22] [c21] [j28] [j27] [c19] [c14] [c11] [j18]
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